31 #define DSI_PHY_RSTZ			0xa0
32 #define PHY_DISFORCEPLL			0
34 #define PHY_DISABLECLK			0
36 #define PHY_RSTZ			0
38 #define PHY_SHUTDOWNZ			0
39 #define PHY_UNSHUTDOWNZ			BIT(0)
41 #define DSI_PHY_IF_CFG			0xa4
42 #define N_LANES(n)			((((n) - 1) & 0x3) << 0)
43 #define PHY_STOP_WAIT_TIME(cycle)	(((cycle) & 0xff) << 8)
45 #define DSI_PHY_STATUS			0xb0
46 #define LOCK				BIT(0)
49 #define DSI_PHY_TST_CTRL0		0xb4
51 #define PHY_UNTESTCLK			0
52 #define PHY_TESTCLR			BIT(0)
53 #define PHY_UNTESTCLR			0
55 #define DSI_PHY_TST_CTRL1		0xb8
57 #define PHY_UNTESTEN			0
58 #define PHY_TESTDOUT(n)			(((n) & 0xff) << 8)
59 #define PHY_TESTDIN(n)			(((n) & 0xff) << 0)
61 #define DSI_INT_ST0			0xbc
62 #define DSI_INT_ST1			0xc0
63 #define DSI_INT_MSK0			0xc4
64 #define DSI_INT_MSK1			0xc8
70 #define VCO_RANGE_CON_SEL(val)	(((val) & 0x7) << 3)
71 #define VCO_IN_CAP_CON_DEFAULT	(0x0 << 1)
72 #define VCO_IN_CAP_CON_LOW	(0x1 << 1)
73 #define VCO_IN_CAP_CON_HIGH	(0x2 << 1)
74 #define REF_BIAS_CUR_SEL	BIT(0)
76 #define CP_CURRENT_3UA	0x1
77 #define CP_CURRENT_4_5UA	0x2
78 #define CP_CURRENT_7_5UA	0x6
79 #define CP_CURRENT_6UA	0x9
80 #define CP_CURRENT_12UA	0xb
81 #define CP_CURRENT_SEL(val)	((val) & 0xf)
84 #define LPF_RESISTORS_15_5KOHM	0x1
85 #define LPF_RESISTORS_13KOHM	0x2
86 #define LPF_RESISTORS_11_5KOHM	0x4
87 #define LPF_RESISTORS_10_5KOHM	0x8
88 #define LPF_RESISTORS_8KOHM	0x10
90 #define LPF_RESISTORS_SEL(val)	((val) & 0x3f)
92 #define HSFREQRANGE_SEL(val)	(((val) & 0x3f) << 1)
94 #define INPUT_DIVIDER(val)	(((val) - 1) & 0x7f)
95 #define LOW_PROGRAM_EN		0
97 #define LOOP_DIV_LOW_SEL(val)	(((val) - 1) & 0x1f)
98 #define LOOP_DIV_HIGH_SEL(val)	((((val) - 1) >> 5) & 0xf)
105 #define BANDGAP_ON		BIT(0)
108 #define	TER_RESISTOR_LOW	0
111 #define SETRD_MAX		(0x7 << 2)
113 #define TER_RESISTORS_ON	BIT(0)
115 #define BIASEXTR_SEL(val)	((val) & 0x7)
116 #define BANDGAP_SEL(val)	((val) & 0x7)
121 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL		0x10
122 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS			0x11
123 #define PLL_LPF_AND_CP_CONTROL				0x12
124 #define PLL_INPUT_DIVIDER_RATIO				0x17
125 #define PLL_LOOP_DIVIDER_RATIO				0x18
126 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL	0x19
127 #define BANDGAP_AND_BIAS_CONTROL			0x20
128 #define TERMINATION_RESISTER_CONTROL			0x21
129 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY		0x22
130 #define HS_RX_CONTROL_OF_LANE_CLK			0x34
131 #define HS_RX_CONTROL_OF_LANE_0				0x44
132 #define HS_RX_CONTROL_OF_LANE_1				0x54
133 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL	0x60
134 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL	0x61
135 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL	0x62
136 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL	0x63
137 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL	0x64
138 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL		0x65
139 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL	0x70
140 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL	0x71
141 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL	0x72
142 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL	0x73
143 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL		0x74
144 #define HS_RX_DATA_LANE_THS_SETTLE_CONTROL		0x75
145 #define HS_RX_CONTROL_OF_LANE_2				0x84
146 #define HS_RX_CONTROL_OF_LANE_3				0x94
148 #define DW_MIPI_NEEDS_PHY_CFG_CLK	BIT(0)
151 #define PX30_GRF_PD_VO_CON1		0x0438
152 #define PX30_DSI_FORCETXSTOPMODE	(0xf << 7)
155 #define PX30_DSI_LCDC_SEL		BIT(0)
157 #define RK3288_GRF_SOC_CON6		0x025c
161 #define RK3399_GRF_SOC_CON20		0x6250
162 #define RK3399_DSI0_LCDC_SEL		BIT(0)
165 #define RK3399_GRF_SOC_CON22		0x6258
166 #define RK3399_DSI0_TURNREQUEST		(0xf << 12)
167 #define RK3399_DSI0_TURNDISABLE		(0xf << 8)
168 #define RK3399_DSI0_FORCETXSTOPMODE	(0xf << 4)
169 #define RK3399_DSI0_FORCERXMODE		(0xf << 0)
171 #define RK3399_GRF_SOC_CON23		0x625c
172 #define RK3399_DSI1_TURNDISABLE		(0xf << 12)
173 #define RK3399_DSI1_FORCETXSTOPMODE	(0xf << 8)
174 #define RK3399_DSI1_FORCERXMODE		(0xf << 4)
175 #define RK3399_DSI1_ENABLE		(0xf << 0)
177 #define RK3399_GRF_SOC_CON24		0x6260
182 #define RK3399_TXRX_TURNREQUEST		GENMASK(3, 0)
184 #define RK3568_GRF_VO_CON2		0x0368
185 #define RK3568_DSI0_SKEWCALHS		(0x1f << 11)
186 #define RK3568_DSI0_FORCETXSTOPMODE	(0xf << 4)
188 #define RK3568_DSI0_FORCERXMODE		BIT(0)
195 #define RK3568_GRF_VO_CON3		0x36c
196 #define RK3568_DSI1_SKEWCALHS		(0x1f << 11)
197 #define RK3568_DSI1_FORCETXSTOPMODE	(0xf << 4)
199 #define RK3568_DSI1_FORCERXMODE		BIT(0)
307 	{  89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
308 	{  99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
309 	{ 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
310 	{ 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
311 	{ 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
312 	{ 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
313 	{ 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
314 	{ 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
315 	{ 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
316 	{ 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
317 	{ 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
318 	{ 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
319 	{ 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
320 	{ 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
321 	{ 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
322 	{ 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
323 	{ 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
324 	{ 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
325 	{ 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
326 	{ 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
327 	{ 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
328 	{ 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
329 	{ 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
330 	{ 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
331 	{ 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
332 	{ 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
333 	{ 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
334 	{ 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
335 	{ 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
336 	{1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
337 	{1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
338 	{1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
339 	{1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
340 	{1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
341 	{1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
342 	{1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
343 	{1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
344 	{1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
345 	{1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }
352 	for (i = 0; i < ARRAY_SIZE(dppa_map); i++)  in max_mbps_to_parameter()
369 	 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content  in dw_mipi_dsi_phy_write()
375 	dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |  in dw_mipi_dsi_phy_write()
380 	dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |  in dw_mipi_dsi_phy_write()
408 		return 0;  in dw_mipi_dsi_phy_init()
422 	vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;  in dw_mipi_dsi_phy_init()
425 	if (i < 0) {  in dw_mipi_dsi_phy_init()
550 	unsigned long best_freq = 0;  in dw_mipi_dsi_get_lane_mbps()
559 	if (bpp < 0) {  in dw_mipi_dsi_get_lane_mbps()
585 		return 0;  in dw_mipi_dsi_get_lane_mbps()
640 	return 0;  in dw_mipi_dsi_get_lane_mbps()
708 	for (i = 0; i < ARRAY_SIZE(hstt_table); i++)  in dw_mipi_dsi_phy_get_timing()
717 	return 0;  in dw_mipi_dsi_phy_get_timing()
778 	return 0;  in dw_mipi_dsi_encoder_atomic_check()
788 	if (mux < 0)  in dw_mipi_dsi_encoder_enable()
832 	return 0;  in rockchip_dsi_drm_create_encoder()
843 	local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0);  in dw_mipi_dsi_rockchip_find_second()
855 		remote = of_graph_get_remote_node(node, 1, 0);  in dw_mipi_dsi_rockchip_find_second()
928 			return 0;  in dw_mipi_dsi_rockchip_bind()
976 						  dev->of_node, 0, 0);  in dw_mipi_dsi_rockchip_bind()
986 	return 0;  in dw_mipi_dsi_rockchip_bind()
1063 	return 0;  in dw_mipi_dsi_rockchip_host_attach()
1088 	return 0;  in dw_mipi_dsi_rockchip_host_detach()
1106 	return 0;  in dw_mipi_dsi_rockchip_dphy_bind()
1138 	if (ret < 0)  in dw_mipi_dsi_dphy_init()
1143 		if (ret < 0)  in dw_mipi_dsi_dphy_init()
1155 		if (ret < 0)  in dw_mipi_dsi_dphy_init()
1159 	return 0;  in dw_mipi_dsi_dphy_init()
1181 	return 0;  in dw_mipi_dsi_dphy_exit()
1197 	return 0;  in dw_mipi_dsi_dphy_configure()
1209 	if (i < 0) {  in dw_mipi_dsi_dphy_power_on()
1216 	if (ret < 0) {  in dw_mipi_dsi_dphy_power_on()
1242 		if (ret < 0) {  in dw_mipi_dsi_dphy_power_on()
1250 	 * Set clock lane and hsfreqrange by lane0(test code 0x44)  in dw_mipi_dsi_dphy_power_on()
1252 	dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0);  in dw_mipi_dsi_dphy_power_on()
1255 	dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0);  in dw_mipi_dsi_dphy_power_on()
1256 	dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0);  in dw_mipi_dsi_dphy_power_on()
1257 	dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0);  in dw_mipi_dsi_dphy_power_on()
1260 	dw_mipi_dsi_phy_write(dsi, 0x0, 0);  in dw_mipi_dsi_dphy_power_on()
1291 		if (ret < 0)  in dw_mipi_dsi_dphy_power_off()
1334 	return 0;  in dw_mipi_dsi_rockchip_resume()
1356 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in dw_mipi_dsi_rockchip_probe()
1363 	i = 0;  in dw_mipi_dsi_rockchip_probe()
1465 	return 0;  in dw_mipi_dsi_rockchip_probe()
1477 		.reg = 0xff450000,
1479 		.lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1484 		.lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1495 		.reg = 0xff960000,
1497 		.lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1503 		.reg = 0xff964000,
1505 		.lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1522 		     HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0));  in rk3399_dphy_tx1rx1_init()
1524 		     HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));  in rk3399_dphy_tx1rx1_init()
1526 		     HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR));  in rk3399_dphy_tx1rx1_init()
1528 		     HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));  in rk3399_dphy_tx1rx1_init()
1530 	return 0;  in rk3399_dphy_tx1rx1_init()
1542 		     HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));  in rk3399_dphy_tx1rx1_power_on()
1547 		     HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE));  in rk3399_dphy_tx1rx1_power_on()
1549 		     HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE));  in rk3399_dphy_tx1rx1_power_on()
1553 		     HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST));  in rk3399_dphy_tx1rx1_power_on()
1564 		     HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0),  in rk3399_dphy_tx1rx1_power_on()
1569 	return 0;  in rk3399_dphy_tx1rx1_power_on()
1577 		     HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));  in rk3399_dphy_tx1rx1_power_off()
1579 	return 0;  in rk3399_dphy_tx1rx1_power_off()
1584 		.reg = 0xff960000,
1586 		.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1591 		.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
1600 		.reg = 0xff968000,
1602 		.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
1607 		.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
1634 		.reg = 0xfe060000,
1636 		.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS |
1643 		.reg = 0xfe070000,
1645 		.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS |