Lines Matching refs:rdev
1725 static int si_populate_voltage_value(struct radeon_device *rdev,
1728 static int si_get_std_voltage_value(struct radeon_device *rdev,
1731 static int si_write_smc_soft_register(struct radeon_device *rdev,
1733 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1736 static int si_calculate_sclk_params(struct radeon_device *rdev,
1740 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1741 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1743 static struct si_power_info *si_get_pi(struct radeon_device *rdev) in si_get_pi() argument
1745 struct si_power_info *pi = rdev->pm.dpm.priv; in si_get_pi()
1777 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, in si_calculate_leakage_for_v_and_t() argument
1805 static void si_calculate_leakage_for_v(struct radeon_device *rdev, in si_calculate_leakage_for_v() argument
1816 static void si_update_dte_from_pl2(struct radeon_device *rdev, in si_update_dte_from_pl2() argument
1819 u32 p_limit1 = rdev->pm.dpm.tdp_limit; in si_update_dte_from_pl2()
1820 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; in si_update_dte_from_pl2()
1846 static void si_initialize_powertune_defaults(struct radeon_device *rdev) in si_initialize_powertune_defaults() argument
1848 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_initialize_powertune_defaults()
1849 struct si_power_info *si_pi = si_get_pi(rdev); in si_initialize_powertune_defaults()
1852 if (rdev->family == CHIP_TAHITI) { in si_initialize_powertune_defaults()
1859 switch (rdev->pdev->device) { in si_initialize_powertune_defaults()
1886 } else if (rdev->family == CHIP_PITCAIRN) { in si_initialize_powertune_defaults()
1887 switch (rdev->pdev->device) { in si_initialize_powertune_defaults()
1923 } else if (rdev->family == CHIP_VERDE) { in si_initialize_powertune_defaults()
1928 switch (rdev->pdev->device) { in si_initialize_powertune_defaults()
1975 } else if (rdev->family == CHIP_OLAND) { in si_initialize_powertune_defaults()
1976 switch (rdev->pdev->device) { in si_initialize_powertune_defaults()
2025 } else if (rdev->family == CHIP_HAINAN) { in si_initialize_powertune_defaults()
2048 si_update_dte_from_pl2(rdev, &si_pi->dte_data); in si_initialize_powertune_defaults()
2072 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) in si_get_smc_power_scaling_factor() argument
2077 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) in si_calculate_cac_wintime() argument
2084 xclk = radeon_get_xclk(rdev); in si_calculate_cac_wintime()
2102 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, in si_calculate_adjusted_tdp_limits() argument
2110 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) in si_calculate_adjusted_tdp_limits()
2113 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2116 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2117 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); in si_calculate_adjusted_tdp_limits()
2119 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2120 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; in si_calculate_adjusted_tdp_limits()
2121 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) in si_calculate_adjusted_tdp_limits()
2122 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; in si_calculate_adjusted_tdp_limits()
2135 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, in si_populate_smc_tdp_limits() argument
2138 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_populate_smc_tdp_limits()
2139 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_smc_tdp_limits()
2144 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; in si_populate_smc_tdp_limits()
2145 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); in si_populate_smc_tdp_limits()
2155 ret = si_calculate_adjusted_tdp_limits(rdev, in si_populate_smc_tdp_limits()
2157 rdev->pm.dpm.tdp_adjustment, in si_populate_smc_tdp_limits()
2170 ret = si_copy_bytes_to_smc(rdev, in si_populate_smc_tdp_limits()
2189 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, in si_populate_smc_tdp_limits()
2200 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, in si_populate_smc_tdp_limits_2() argument
2203 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_populate_smc_tdp_limits_2()
2204 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_smc_tdp_limits_2()
2208 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); in si_populate_smc_tdp_limits_2()
2214 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); in si_populate_smc_tdp_limits_2()
2216 …cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_… in si_populate_smc_tdp_limits_2()
2218 ret = si_copy_bytes_to_smc(rdev, in si_populate_smc_tdp_limits_2()
2232 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, in si_calculate_power_efficiency_ratio() argument
2254 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, in si_should_disable_uvd_powertune() argument
2257 struct si_power_info *si_pi = si_get_pi(rdev); in si_should_disable_uvd_powertune()
2266 static int si_populate_power_containment_values(struct radeon_device *rdev, in si_populate_power_containment_values() argument
2270 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_populate_power_containment_values()
2271 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_populate_power_containment_values()
2294 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); in si_populate_power_containment_values()
2329 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_power_containment_values()
2334 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); in si_populate_power_containment_values()
2338 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_power_containment_values()
2343 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); in si_populate_power_containment_values()
2347 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, in si_populate_power_containment_values()
2360 static int si_populate_sq_ramping_values(struct radeon_device *rdev, in si_populate_sq_ramping_values() argument
2364 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_populate_sq_ramping_values()
2376 if (rdev->pm.dpm.sq_ramping_threshold == 0) in si_populate_sq_ramping_values()
2398 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
2417 static int si_enable_power_containment(struct radeon_device *rdev, in si_enable_power_containment() argument
2421 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_enable_power_containment()
2427 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { in si_enable_power_containment()
2428 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); in si_enable_power_containment()
2437 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); in si_enable_power_containment()
2447 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) in si_initialize_smc_dte_tables() argument
2449 struct si_power_info *si_pi = si_get_pi(rdev); in si_initialize_smc_dte_tables()
2505 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, in si_initialize_smc_dte_tables()
2512 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, in si_get_cac_std_voltage_max_min() argument
2515 struct si_power_info *si_pi = si_get_pi(rdev); in si_get_cac_std_voltage_max_min()
2517 &rdev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
2557 static int si_init_dte_leakage_table(struct radeon_device *rdev, in si_init_dte_leakage_table() argument
2562 struct si_power_info *si_pi = si_get_pi(rdev); in si_init_dte_leakage_table()
2570 scaling_factor = si_get_smc_power_scaling_factor(rdev); in si_init_dte_leakage_table()
2578 si_calculate_leakage_for_v_and_t(rdev, in si_init_dte_leakage_table()
2597 static int si_init_simplified_leakage_table(struct radeon_device *rdev, in si_init_simplified_leakage_table() argument
2601 struct si_power_info *si_pi = si_get_pi(rdev); in si_init_simplified_leakage_table()
2608 scaling_factor = si_get_smc_power_scaling_factor(rdev); in si_init_simplified_leakage_table()
2613 si_calculate_leakage_for_v(rdev, in si_init_simplified_leakage_table()
2632 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) in si_initialize_smc_cac_tables() argument
2634 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_initialize_smc_cac_tables()
2635 struct si_power_info *si_pi = si_get_pi(rdev); in si_initialize_smc_cac_tables()
2641 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; in si_initialize_smc_cac_tables()
2654 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; in si_initialize_smc_cac_tables()
2657 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); in si_initialize_smc_cac_tables()
2662 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); in si_initialize_smc_cac_tables()
2672 ret = si_init_dte_leakage_table(rdev, cac_tables, in si_initialize_smc_cac_tables()
2676 ret = si_init_simplified_leakage_table(rdev, cac_tables, in si_initialize_smc_cac_tables()
2681 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; in si_initialize_smc_cac_tables()
2697 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, in si_initialize_smc_cac_tables()
2703 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); in si_initialize_smc_cac_tables()
2716 static int si_program_cac_config_registers(struct radeon_device *rdev, in si_program_cac_config_registers() argument
2755 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) in si_initialize_hardware_cac_manager() argument
2757 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_initialize_hardware_cac_manager()
2758 struct si_power_info *si_pi = si_get_pi(rdev); in si_initialize_hardware_cac_manager()
2765 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); in si_initialize_hardware_cac_manager()
2768 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); in si_initialize_hardware_cac_manager()
2771 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); in si_initialize_hardware_cac_manager()
2778 static int si_enable_smc_cac(struct radeon_device *rdev, in si_enable_smc_cac() argument
2782 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_enable_smc_cac()
2783 struct si_power_info *si_pi = si_get_pi(rdev); in si_enable_smc_cac()
2789 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { in si_enable_smc_cac()
2791 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); in si_enable_smc_cac()
2796 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); in si_enable_smc_cac()
2805 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); in si_enable_smc_cac()
2812 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); in si_enable_smc_cac()
2814 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); in si_enable_smc_cac()
2819 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); in si_enable_smc_cac()
2825 static int si_init_smc_spll_table(struct radeon_device *rdev) in si_init_smc_spll_table() argument
2827 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_init_smc_spll_table()
2828 struct si_power_info *si_pi = si_get_pi(rdev); in si_init_smc_spll_table()
2846 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); in si_init_smc_spll_table()
2884 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, in si_init_smc_spll_table()
2896 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, in si_get_lower_of_leakage_and_vce_voltage() argument
2900 struct si_power_info *si_pi = si_get_pi(rdev); in si_get_lower_of_leakage_and_vce_voltage()
2914 static int si_get_vce_clock_voltage(struct radeon_device *rdev, in si_get_vce_clock_voltage() argument
2920 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in si_get_vce_clock_voltage()
2941 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); in si_get_vce_clock_voltage()
2946 static void si_apply_state_adjust_rules(struct radeon_device *rdev, in si_apply_state_adjust_rules() argument
2959 if (rdev->family == CHIP_HAINAN) { in si_apply_state_adjust_rules()
2960 if ((rdev->pdev->revision == 0x81) || in si_apply_state_adjust_rules()
2961 (rdev->pdev->revision == 0xC3) || in si_apply_state_adjust_rules()
2962 (rdev->pdev->device == 0x6664) || in si_apply_state_adjust_rules()
2963 (rdev->pdev->device == 0x6665) || in si_apply_state_adjust_rules()
2964 (rdev->pdev->device == 0x6667)) { in si_apply_state_adjust_rules()
2967 if ((rdev->pdev->revision == 0xC3) || in si_apply_state_adjust_rules()
2968 (rdev->pdev->device == 0x6665)) { in si_apply_state_adjust_rules()
2972 } else if (rdev->family == CHIP_OLAND) { in si_apply_state_adjust_rules()
2973 if ((rdev->pdev->revision == 0xC7) || in si_apply_state_adjust_rules()
2974 (rdev->pdev->revision == 0x80) || in si_apply_state_adjust_rules()
2975 (rdev->pdev->revision == 0x81) || in si_apply_state_adjust_rules()
2976 (rdev->pdev->revision == 0x83) || in si_apply_state_adjust_rules()
2977 (rdev->pdev->revision == 0x87) || in si_apply_state_adjust_rules()
2978 (rdev->pdev->device == 0x6604) || in si_apply_state_adjust_rules()
2979 (rdev->pdev->device == 0x6605)) { in si_apply_state_adjust_rules()
2983 if (rdev->pm.dpm.high_pixelclock_count > 1) in si_apply_state_adjust_rules()
2988 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in si_apply_state_adjust_rules()
2989 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in si_apply_state_adjust_rules()
2990 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
2997 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in si_apply_state_adjust_rules()
2998 ni_dpm_vblank_too_short(rdev)) in si_apply_state_adjust_rules()
3006 if (rdev->pm.dpm.ac_power) in si_apply_state_adjust_rules()
3007 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_apply_state_adjust_rules()
3009 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in si_apply_state_adjust_rules()
3015 if (rdev->pm.dpm.ac_power == false) { in si_apply_state_adjust_rules()
3029 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3031 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3033 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3078 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in si_apply_state_adjust_rules()
3079 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in si_apply_state_adjust_rules()
3080 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in si_apply_state_adjust_rules()
3081 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in si_apply_state_adjust_rules()
3129 btc_adjust_clock_combinations(rdev, max_limits, in si_apply_state_adjust_rules()
3135 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3138 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3141 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3144 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, in si_apply_state_adjust_rules()
3145 rdev->clock.current_dispclk, in si_apply_state_adjust_rules()
3150 btc_apply_voltage_delta_rules(rdev, in si_apply_state_adjust_rules()
3158 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
3164 static int si_read_smc_soft_register(struct radeon_device *rdev,
3167 struct si_power_info *si_pi = si_get_pi(rdev);
3169 return si_read_smc_sram_dword(rdev,
3175 static int si_write_smc_soft_register(struct radeon_device *rdev, in si_write_smc_soft_register() argument
3178 struct si_power_info *si_pi = si_get_pi(rdev); in si_write_smc_soft_register()
3180 return si_write_smc_sram_dword(rdev, in si_write_smc_soft_register()
3185 static bool si_is_special_1gb_platform(struct radeon_device *rdev) in si_is_special_1gb_platform() argument
3206 if ((rdev->pdev->device == 0x6819) && in si_is_special_1gb_platform()
3213 static void si_get_leakage_vddc(struct radeon_device *rdev) in si_get_leakage_vddc() argument
3215 struct si_power_info *si_pi = si_get_pi(rdev); in si_get_leakage_vddc()
3220 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); in si_get_leakage_vddc()
3232 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, in si_get_leakage_voltage_from_leakage_index() argument
3235 struct si_power_info *si_pi = si_get_pi(rdev); in si_get_leakage_voltage_from_leakage_index()
3259 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) in si_set_dpm_event_sources() argument
3261 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_set_dpm_event_sources()
3294 static void si_enable_auto_throttle_source(struct radeon_device *rdev, in si_enable_auto_throttle_source() argument
3298 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_enable_auto_throttle_source()
3303 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in si_enable_auto_throttle_source()
3308 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in si_enable_auto_throttle_source()
3313 static void si_start_dpm(struct radeon_device *rdev) in si_start_dpm() argument
3318 static void si_stop_dpm(struct radeon_device *rdev) in si_stop_dpm() argument
3323 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) in si_enable_sclk_control() argument
3333 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3339 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3348 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3350 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3355 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3358 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3365 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, in si_send_msg_to_smc_with_parameter() argument
3369 return si_send_msg_to_smc(rdev, msg); in si_send_msg_to_smc_with_parameter()
3372 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) in si_restrict_performance_levels_before_switch() argument
3374 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) in si_restrict_performance_levels_before_switch()
3377 …return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK)… in si_restrict_performance_levels_before_switch()
3381 int si_dpm_force_performance_level(struct radeon_device *rdev, in si_dpm_force_performance_level() argument
3384 struct radeon_ps *rps = rdev->pm.dpm.current_ps; in si_dpm_force_performance_level()
3389 …if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3392 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3395 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3398 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3401 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3404 …if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3408 rdev->pm.dpm.forced_level = level; in si_dpm_force_performance_level()
3414 static int si_set_boot_state(struct radeon_device *rdev)
3416 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3421 static int si_set_sw_state(struct radeon_device *rdev) in si_set_sw_state() argument
3423 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? in si_set_sw_state()
3427 static int si_halt_smc(struct radeon_device *rdev) in si_halt_smc() argument
3429 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) in si_halt_smc()
3432 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? in si_halt_smc()
3436 static int si_resume_smc(struct radeon_device *rdev) in si_resume_smc() argument
3438 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) in si_resume_smc()
3441 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? in si_resume_smc()
3445 static void si_dpm_start_smc(struct radeon_device *rdev) in si_dpm_start_smc() argument
3447 si_program_jump_on_start(rdev); in si_dpm_start_smc()
3448 si_start_smc(rdev); in si_dpm_start_smc()
3449 si_start_smc_clock(rdev); in si_dpm_start_smc()
3452 static void si_dpm_stop_smc(struct radeon_device *rdev) in si_dpm_stop_smc() argument
3454 si_reset_smc(rdev); in si_dpm_stop_smc()
3455 si_stop_smc_clock(rdev); in si_dpm_stop_smc()
3458 static int si_process_firmware_header(struct radeon_device *rdev) in si_process_firmware_header() argument
3460 struct si_power_info *si_pi = si_get_pi(rdev); in si_process_firmware_header()
3464 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3473 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3482 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3491 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3500 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3509 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3518 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3527 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3536 ret = si_read_smc_sram_dword(rdev, in si_process_firmware_header()
3548 static void si_read_clock_registers(struct radeon_device *rdev) in si_read_clock_registers() argument
3550 struct si_power_info *si_pi = si_get_pi(rdev); in si_read_clock_registers()
3569 static void si_enable_thermal_protection(struct radeon_device *rdev, in si_enable_thermal_protection() argument
3578 static void si_enable_acpi_power_management(struct radeon_device *rdev) in si_enable_acpi_power_management() argument
3584 static int si_enter_ulp_state(struct radeon_device *rdev)
3593 static int si_exit_ulp_state(struct radeon_device *rdev)
3601 for (i = 0; i < rdev->usec_timeout; i++) {
3611 static int si_notify_smc_display_change(struct radeon_device *rdev, in si_notify_smc_display_change() argument
3617 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? in si_notify_smc_display_change()
3621 static void si_program_response_times(struct radeon_device *rdev) in si_program_response_times() argument
3627 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); in si_program_response_times()
3629 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; in si_program_response_times()
3637 reference_clock = radeon_get_xclk(rdev); in si_program_response_times()
3643 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); in si_program_response_times()
3644 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); in si_program_response_times()
3645 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); in si_program_response_times()
3646 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); in si_program_response_times()
3649 static void si_program_ds_registers(struct radeon_device *rdev) in si_program_ds_registers() argument
3651 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_program_ds_registers()
3661 static void si_program_display_gap(struct radeon_device *rdev) in si_program_display_gap() argument
3667 if (rdev->pm.dpm.new_active_crtc_count > 0) in si_program_display_gap()
3672 if (rdev->pm.dpm.new_active_crtc_count > 1) in si_program_display_gap()
3682 if ((rdev->pm.dpm.new_active_crtc_count > 0) && in si_program_display_gap()
3683 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { in si_program_display_gap()
3685 for (i = 0; i < rdev->num_crtc; i++) { in si_program_display_gap()
3686 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) in si_program_display_gap()
3689 if (i == rdev->num_crtc) in si_program_display_gap()
3703 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); in si_program_display_gap()
3706 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) in si_enable_spread_spectrum() argument
3708 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_enable_spread_spectrum()
3719 static void si_setup_bsp(struct radeon_device *rdev) in si_setup_bsp() argument
3721 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_setup_bsp()
3722 u32 xclk = radeon_get_xclk(rdev); in si_setup_bsp()
3743 static void si_program_git(struct radeon_device *rdev) in si_program_git() argument
3748 static void si_program_tp(struct radeon_device *rdev) in si_program_tp() argument
3768 static void si_program_tpp(struct radeon_device *rdev) in si_program_tpp() argument
3773 static void si_program_sstp(struct radeon_device *rdev) in si_program_sstp() argument
3778 static void si_enable_display_gap(struct radeon_device *rdev) in si_enable_display_gap() argument
3792 static void si_program_vc(struct radeon_device *rdev) in si_program_vc() argument
3794 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_program_vc()
3799 static void si_clear_vc(struct radeon_device *rdev) in si_clear_vc() argument
3839 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) in si_get_strobe_mode_settings() argument
3841 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_get_strobe_mode_settings()
3859 static int si_upload_firmware(struct radeon_device *rdev) in si_upload_firmware() argument
3861 struct si_power_info *si_pi = si_get_pi(rdev); in si_upload_firmware()
3864 si_reset_smc(rdev); in si_upload_firmware()
3865 si_stop_smc_clock(rdev); in si_upload_firmware()
3867 ret = si_load_smc_ucode(rdev, si_pi->sram_end); in si_upload_firmware()
3872 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, in si_validate_phase_shedding_tables() argument
3899 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, in si_trim_voltage_table_to_fit_state_table() argument
3916 static int si_get_svi2_voltage_table(struct radeon_device *rdev, in si_get_svi2_voltage_table() argument
3937 static int si_construct_voltage_tables(struct radeon_device *rdev) in si_construct_voltage_tables() argument
3939 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_construct_voltage_tables()
3940 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_construct_voltage_tables()
3941 struct si_power_info *si_pi = si_get_pi(rdev); in si_construct_voltage_tables()
3945 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, in si_construct_voltage_tables()
3951 si_trim_voltage_table_to_fit_state_table(rdev, in si_construct_voltage_tables()
3955 ret = si_get_svi2_voltage_table(rdev, in si_construct_voltage_tables()
3956 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_construct_voltage_tables()
3965 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, in si_construct_voltage_tables()
3971 si_trim_voltage_table_to_fit_state_table(rdev, in si_construct_voltage_tables()
3976 ret = si_get_svi2_voltage_table(rdev, in si_construct_voltage_tables()
3977 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_construct_voltage_tables()
3984 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, in si_construct_voltage_tables()
3998 si_trim_voltage_table_to_fit_state_table(rdev, in si_construct_voltage_tables()
4004 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, in si_construct_voltage_tables()
4017 static void si_populate_smc_voltage_table(struct radeon_device *rdev, in si_populate_smc_voltage_table() argument
4027 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, in si_populate_smc_voltage_tables() argument
4030 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_smc_voltage_tables()
4031 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_populate_smc_voltage_tables()
4032 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_smc_voltage_tables()
4036 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, in si_populate_smc_voltage_tables()
4038 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, in si_populate_smc_voltage_tables()
4040 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, in si_populate_smc_voltage_tables()
4044 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); in si_populate_smc_voltage_tables()
4057 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); in si_populate_smc_voltage_tables()
4065 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); in si_populate_smc_voltage_tables()
4072 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, in si_populate_smc_voltage_tables()
4073 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { in si_populate_smc_voltage_tables()
4074 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); in si_populate_smc_voltage_tables()
4079 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, in si_populate_smc_voltage_tables()
4090 static int si_populate_voltage_value(struct radeon_device *rdev, in si_populate_voltage_value() argument
4110 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, in si_populate_mvdd_value() argument
4113 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_mvdd_value()
4114 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_mvdd_value()
4127 static int si_get_std_voltage_value(struct radeon_device *rdev, in si_get_std_voltage_value() argument
4135 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { in si_get_std_voltage_value()
4136 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { in si_get_std_voltage_value()
4137 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value()
4140 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4142 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4144 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4146 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4149 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4155 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4157 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4159 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4161 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4164 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4170 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4171 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; in si_get_std_voltage_value()
4178 static int si_populate_std_voltage_value(struct radeon_device *rdev, in si_populate_std_voltage_value() argument
4188 static int si_populate_phase_shedding_value(struct radeon_device *rdev, in si_populate_phase_shedding_value() argument
4207 static int si_init_arb_table_index(struct radeon_device *rdev) in si_init_arb_table_index() argument
4209 struct si_power_info *si_pi = si_get_pi(rdev); in si_init_arb_table_index()
4213 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); in si_init_arb_table_index()
4220 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); in si_init_arb_table_index()
4223 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) in si_initial_switch_from_arb_f0_to_f1() argument
4225 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); in si_initial_switch_from_arb_f0_to_f1()
4228 static int si_reset_to_default(struct radeon_device *rdev) in si_reset_to_default() argument
4230 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? in si_reset_to_default()
4234 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) in si_force_switch_to_arb_f0() argument
4236 struct si_power_info *si_pi = si_get_pi(rdev); in si_force_switch_to_arb_f0()
4240 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, in si_force_switch_to_arb_f0()
4250 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); in si_force_switch_to_arb_f0()
4253 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, in si_calculate_memory_refresh_rate() argument
4272 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, in si_populate_memory_timing_parameters() argument
4281 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); in si_populate_memory_timing_parameters()
4283 radeon_atom_set_engine_dram_timings(rdev, in si_populate_memory_timing_parameters()
4298 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, in si_do_program_memory_timing_parameters() argument
4302 struct si_power_info *si_pi = si_get_pi(rdev); in si_do_program_memory_timing_parameters()
4308 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); in si_do_program_memory_timing_parameters()
4311 ret = si_copy_bytes_to_smc(rdev, in si_do_program_memory_timing_parameters()
4325 static int si_program_memory_timing_parameters(struct radeon_device *rdev, in si_program_memory_timing_parameters() argument
4328 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, in si_program_memory_timing_parameters()
4332 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, in si_populate_initial_mvdd_value() argument
4335 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_initial_mvdd_value()
4336 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_initial_mvdd_value()
4339 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, in si_populate_initial_mvdd_value()
4345 static int si_populate_smc_initial_state(struct radeon_device *rdev, in si_populate_smc_initial_state() argument
4350 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_smc_initial_state()
4351 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_populate_smc_initial_state()
4352 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_smc_initial_state()
4399 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_smc_initial_state()
4406 ret = si_get_std_voltage_value(rdev, in si_populate_smc_initial_state()
4410 si_populate_std_voltage_value(rdev, std_vddc, in si_populate_smc_initial_state()
4416 si_populate_voltage_value(rdev, in si_populate_smc_initial_state()
4422 si_populate_phase_shedding_value(rdev, in si_populate_smc_initial_state()
4423 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_initial_state()
4429 si_populate_initial_mvdd_value(rdev, &table->initialState.level.mvdd); in si_populate_smc_initial_state()
4440 si_get_strobe_mode_settings(rdev, in si_populate_smc_initial_state()
4468 static int si_populate_smc_acpi_state(struct radeon_device *rdev, in si_populate_smc_acpi_state() argument
4471 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_smc_acpi_state()
4472 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_populate_smc_acpi_state()
4473 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_smc_acpi_state()
4493 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_smc_acpi_state()
4498 ret = si_get_std_voltage_value(rdev, in si_populate_smc_acpi_state()
4501 si_populate_std_voltage_value(rdev, std_vddc, in si_populate_smc_acpi_state()
4508 si_populate_phase_shedding_value(rdev, in si_populate_smc_acpi_state()
4509 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
4516 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_smc_acpi_state()
4521 ret = si_get_std_voltage_value(rdev, in si_populate_smc_acpi_state()
4525 si_populate_std_voltage_value(rdev, std_vddc, in si_populate_smc_acpi_state()
4529 table->ACPIState.level.gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, in si_populate_smc_acpi_state()
4535 si_populate_phase_shedding_value(rdev, in si_populate_smc_acpi_state()
4536 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
4545 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, in si_populate_smc_acpi_state()
4589 si_populate_mvdd_value(rdev, 0, &table->ACPIState.level.mvdd); in si_populate_smc_acpi_state()
4609 static int si_populate_ulv_state(struct radeon_device *rdev, in si_populate_ulv_state() argument
4612 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_populate_ulv_state()
4613 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_ulv_state()
4618 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, in si_populate_ulv_state()
4640 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) in si_program_ulv_memory_timing_parameters() argument
4642 struct si_power_info *si_pi = si_get_pi(rdev); in si_program_ulv_memory_timing_parameters()
4647 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, in si_program_ulv_memory_timing_parameters()
4652 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, in si_program_ulv_memory_timing_parameters()
4655 ret = si_copy_bytes_to_smc(rdev, in si_program_ulv_memory_timing_parameters()
4666 static void si_get_mvdd_configuration(struct radeon_device *rdev) in si_get_mvdd_configuration() argument
4668 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_get_mvdd_configuration()
4673 static int si_init_smc_table(struct radeon_device *rdev) in si_init_smc_table() argument
4675 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_init_smc_table()
4676 struct si_power_info *si_pi = si_get_pi(rdev); in si_init_smc_table()
4677 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; in si_init_smc_table()
4684 si_populate_smc_voltage_tables(rdev, table); in si_init_smc_table()
4686 switch (rdev->pm.int_thermal_type) { in si_init_smc_table()
4699 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in si_init_smc_table()
4702 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { in si_init_smc_table()
4703 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) in si_init_smc_table()
4707 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in si_init_smc_table()
4713 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) in si_init_smc_table()
4716 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { in si_init_smc_table()
4718 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; in si_init_smc_table()
4719 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, in si_init_smc_table()
4723 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); in si_init_smc_table()
4727 ret = si_populate_smc_acpi_state(rdev, table); in si_init_smc_table()
4735 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, in si_init_smc_table()
4741 ret = si_populate_ulv_state(rdev, &table->ULVState); in si_init_smc_table()
4745 ret = si_program_ulv_memory_timing_parameters(rdev); in si_init_smc_table()
4752 lane_width = radeon_get_pcie_lanes(rdev); in si_init_smc_table()
4753 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
4758 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, in si_init_smc_table()
4763 static int si_calculate_sclk_params(struct radeon_device *rdev, in si_calculate_sclk_params() argument
4767 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_calculate_sclk_params()
4768 struct si_power_info *si_pi = si_get_pi(rdev); in si_calculate_sclk_params()
4777 u32 reference_clock = rdev->clock.spll.reference_freq; in si_calculate_sclk_params()
4782 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in si_calculate_sclk_params()
4808 if (radeon_atombios_get_asic_ss_info(rdev, &ss, in si_calculate_sclk_params()
4833 static int si_populate_sclk_value(struct radeon_device *rdev, in si_populate_sclk_value() argument
4840 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); in si_populate_sclk_value()
4854 static int si_populate_mclk_value(struct radeon_device *rdev, in si_populate_mclk_value() argument
4861 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_mclk_value()
4862 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_mclk_value()
4875 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); in si_populate_mclk_value()
4899 u32 reference_clock = rdev->clock.mpll.reference_freq; in si_populate_mclk_value()
4908 if (radeon_atombios_get_asic_ss_info(rdev, &ss, in si_populate_mclk_value()
4943 static void si_populate_smc_sp(struct radeon_device *rdev, in si_populate_smc_sp() argument
4948 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_smc_sp()
4958 static int si_convert_power_level_to_smc(struct radeon_device *rdev, in si_convert_power_level_to_smc() argument
4962 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_convert_power_level_to_smc()
4963 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_convert_power_level_to_smc()
4964 struct si_power_info *si_pi = si_get_pi(rdev); in si_convert_power_level_to_smc()
4976 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); in si_convert_power_level_to_smc()
4986 (rdev->pm.dpm.new_active_crtc_count <= 2)) { in si_convert_power_level_to_smc()
5000 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); in si_convert_power_level_to_smc()
5012 level->strobeMode = si_get_strobe_mode_settings(rdev, in si_convert_power_level_to_smc()
5018 ret = si_populate_mclk_value(rdev, in si_convert_power_level_to_smc()
5026 ret = si_populate_voltage_value(rdev, in si_convert_power_level_to_smc()
5033 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); in si_convert_power_level_to_smc()
5037 ret = si_populate_std_voltage_value(rdev, std_vddc, in si_convert_power_level_to_smc()
5043 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, in si_convert_power_level_to_smc()
5050 ret = si_populate_phase_shedding_value(rdev, in si_convert_power_level_to_smc()
5051 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_convert_power_level_to_smc()
5062 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); in si_convert_power_level_to_smc()
5067 static int si_populate_smc_t(struct radeon_device *rdev, in si_populate_smc_t() argument
5071 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_populate_smc_t()
5116 static int si_disable_ulv(struct radeon_device *rdev) in si_disable_ulv() argument
5118 struct si_power_info *si_pi = si_get_pi(rdev); in si_disable_ulv()
5122 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? in si_disable_ulv()
5128 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, in si_is_state_ulv_compatible() argument
5131 const struct si_power_info *si_pi = si_get_pi(rdev); in si_is_state_ulv_compatible()
5141 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { in si_is_state_ulv_compatible()
5142 if (rdev->clock.current_dispclk <= in si_is_state_ulv_compatible()
5143 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { in si_is_state_ulv_compatible()
5145 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) in si_is_state_ulv_compatible()
5156 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, in si_set_power_state_conditionally_enable_ulv() argument
5159 const struct si_power_info *si_pi = si_get_pi(rdev); in si_set_power_state_conditionally_enable_ulv()
5163 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) in si_set_power_state_conditionally_enable_ulv()
5164 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? in si_set_power_state_conditionally_enable_ulv()
5170 static int si_convert_power_state_to_smc(struct radeon_device *rdev, in si_convert_power_state_to_smc() argument
5174 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_convert_power_state_to_smc()
5175 struct ni_power_info *ni_pi = ni_get_pi(rdev); in si_convert_power_state_to_smc()
5176 struct si_power_info *si_pi = si_get_pi(rdev); in si_convert_power_state_to_smc()
5209 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], in si_convert_power_state_to_smc()
5233 si_write_smc_soft_register(rdev, in si_convert_power_state_to_smc()
5237 si_populate_smc_sp(rdev, radeon_state, smc_state); in si_convert_power_state_to_smc()
5239 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); in si_convert_power_state_to_smc()
5243 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); in si_convert_power_state_to_smc()
5247 return si_populate_smc_t(rdev, radeon_state, smc_state); in si_convert_power_state_to_smc()
5250 static int si_upload_sw_state(struct radeon_device *rdev, in si_upload_sw_state() argument
5253 struct si_power_info *si_pi = si_get_pi(rdev); in si_upload_sw_state()
5264 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); in si_upload_sw_state()
5268 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, in si_upload_sw_state()
5274 static int si_upload_ulv_state(struct radeon_device *rdev) in si_upload_ulv_state() argument
5276 struct si_power_info *si_pi = si_get_pi(rdev); in si_upload_ulv_state()
5288 ret = si_populate_ulv_state(rdev, smc_state); in si_upload_ulv_state()
5290 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, in si_upload_ulv_state()
5297 static int si_upload_smc_data(struct radeon_device *rdev) in si_upload_smc_data() argument
5302 if (rdev->pm.dpm.new_active_crtc_count == 0) in si_upload_smc_data()
5305 for (i = 0; i < rdev->num_crtc; i++) { in si_upload_smc_data()
5306 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { in si_upload_smc_data()
5307 radeon_crtc = rdev->mode_info.crtcs[i]; in si_upload_smc_data()
5318 if (si_write_smc_soft_register(rdev, in si_upload_smc_data()
5323 if (si_write_smc_soft_register(rdev, in si_upload_smc_data()
5328 if (si_write_smc_soft_register(rdev, in si_upload_smc_data()
5336 static int si_set_mc_special_registers(struct radeon_device *rdev, in si_set_mc_special_registers() argument
5339 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_set_mc_special_registers()
5513 static int si_initialize_mc_reg_table(struct radeon_device *rdev) in si_initialize_mc_reg_table() argument
5515 struct si_power_info *si_pi = si_get_pi(rdev); in si_initialize_mc_reg_table()
5518 u8 module_index = rv770_get_memory_module_index(rdev); in si_initialize_mc_reg_table()
5540 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); in si_initialize_mc_reg_table()
5550 ret = si_set_mc_special_registers(rdev, si_table); in si_initialize_mc_reg_table()
5563 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, in si_populate_mc_reg_addresses() argument
5566 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_mc_reg_addresses()
5597 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, in si_convert_mc_reg_table_entry_to_smc() argument
5601 struct si_power_info *si_pi = si_get_pi(rdev); in si_convert_mc_reg_table_entry_to_smc()
5617 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, in si_convert_mc_reg_table_to_smc() argument
5625 si_convert_mc_reg_table_entry_to_smc(rdev, in si_convert_mc_reg_table_to_smc()
5631 static int si_populate_mc_reg_table(struct radeon_device *rdev, in si_populate_mc_reg_table() argument
5635 struct si_power_info *si_pi = si_get_pi(rdev); in si_populate_mc_reg_table()
5641 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); in si_populate_mc_reg_table()
5643 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); in si_populate_mc_reg_table()
5645 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], in si_populate_mc_reg_table()
5654 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, in si_populate_mc_reg_table()
5662 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); in si_populate_mc_reg_table()
5664 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, in si_populate_mc_reg_table()
5669 static int si_upload_mc_reg_table(struct radeon_device *rdev, in si_upload_mc_reg_table() argument
5673 struct si_power_info *si_pi = si_get_pi(rdev); in si_upload_mc_reg_table()
5681 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); in si_upload_mc_reg_table()
5684 return si_copy_bytes_to_smc(rdev, address, in si_upload_mc_reg_table()
5691 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) in si_enable_voltage_control() argument
5699 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, in si_get_maximum_link_speed() argument
5714 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) in si_get_current_pcie_speed() argument
5724 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, in si_request_link_speed_change_before_state_change() argument
5728 struct si_power_info *si_pi = si_get_pi(rdev); in si_request_link_speed_change_before_state_change()
5729 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); in si_request_link_speed_change_before_state_change()
5733 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); in si_request_link_speed_change_before_state_change()
5743 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) in si_request_link_speed_change_before_state_change()
5750 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) in si_request_link_speed_change_before_state_change()
5755 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); in si_request_link_speed_change_before_state_change()
5764 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, in si_notify_link_speed_change_after_state_change() argument
5768 struct si_power_info *si_pi = si_get_pi(rdev); in si_notify_link_speed_change_after_state_change()
5769 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); in si_notify_link_speed_change_after_state_change()
5781 (si_get_current_pcie_speed(rdev) > 0)) in si_notify_link_speed_change_after_state_change()
5785 radeon_acpi_pcie_performance_request(rdev, request, false); in si_notify_link_speed_change_after_state_change()
5791 static int si_ds_request(struct radeon_device *rdev,
5794 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5798 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5802 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5809 static void si_set_max_cu_value(struct radeon_device *rdev) in si_set_max_cu_value() argument
5811 struct si_power_info *si_pi = si_get_pi(rdev); in si_set_max_cu_value()
5813 if (rdev->family == CHIP_VERDE) { in si_set_max_cu_value()
5814 switch (rdev->pdev->device) { in si_set_max_cu_value()
5850 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, in si_patch_single_dependency_table_based_on_leakage() argument
5859 switch (si_get_leakage_voltage_from_leakage_index(rdev, in si_patch_single_dependency_table_based_on_leakage()
5881 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) in si_patch_dependency_tables_based_on_leakage() argument
5885 ret = si_patch_single_dependency_table_based_on_leakage(rdev, in si_patch_dependency_tables_based_on_leakage()
5886 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
5887 ret = si_patch_single_dependency_table_based_on_leakage(rdev, in si_patch_dependency_tables_based_on_leakage()
5888 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
5889 ret = si_patch_single_dependency_table_based_on_leakage(rdev, in si_patch_dependency_tables_based_on_leakage()
5890 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
5894 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, in si_set_pcie_lane_width_in_smc() argument
5905 radeon_set_pcie_lanes(rdev, new_lane_width); in si_set_pcie_lane_width_in_smc()
5906 lane_width = radeon_get_pcie_lanes(rdev); in si_set_pcie_lane_width_in_smc()
5907 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()
5911 static void si_set_vce_clock(struct radeon_device *rdev, in si_set_vce_clock() argument
5919 vce_v1_0_enable_mgcg(rdev, false); in si_set_vce_clock()
5921 vce_v1_0_enable_mgcg(rdev, true); in si_set_vce_clock()
5922 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in si_set_vce_clock()
5926 void si_dpm_setup_asic(struct radeon_device *rdev) in si_dpm_setup_asic() argument
5930 r = si_mc_load_microcode(rdev); in si_dpm_setup_asic()
5933 rv770_get_memory_type(rdev); in si_dpm_setup_asic()
5934 si_read_clock_registers(rdev); in si_dpm_setup_asic()
5935 si_enable_acpi_power_management(rdev); in si_dpm_setup_asic()
5938 static int si_thermal_enable_alert(struct radeon_device *rdev, in si_thermal_enable_alert() argument
5948 rdev->irq.dpm_thermal = false; in si_thermal_enable_alert()
5949 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); in si_thermal_enable_alert()
5957 rdev->irq.dpm_thermal = true; in si_thermal_enable_alert()
5963 static int si_thermal_set_temperature_range(struct radeon_device *rdev, in si_thermal_set_temperature_range() argument
5982 rdev->pm.dpm.thermal.min_temp = low_temp; in si_thermal_set_temperature_range()
5983 rdev->pm.dpm.thermal.max_temp = high_temp; in si_thermal_set_temperature_range()
5988 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) in si_fan_ctrl_set_static_mode() argument
5990 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_set_static_mode()
6010 static int si_thermal_setup_fan_table(struct radeon_device *rdev) in si_thermal_setup_fan_table() argument
6012 struct si_power_info *si_pi = si_get_pi(rdev); in si_thermal_setup_fan_table()
6022 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6029 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6033 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; in si_thermal_setup_fan_table()
6037 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; in si_thermal_setup_fan_table()
6038 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; in si_thermal_setup_fan_table()
6040 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; in si_thermal_setup_fan_table()
6041 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; in si_thermal_setup_fan_table()
6046 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); in si_thermal_setup_fan_table()
6047 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); in si_thermal_setup_fan_table()
6048 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); in si_thermal_setup_fan_table()
6055 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); in si_thermal_setup_fan_table()
6063 reference_clock = radeon_get_xclk(rdev); in si_thermal_setup_fan_table()
6065 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * in si_thermal_setup_fan_table()
6073 ret = si_copy_bytes_to_smc(rdev, in si_thermal_setup_fan_table()
6081 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6087 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) in si_fan_ctrl_start_smc_fan_control() argument
6089 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_start_smc_fan_control()
6092 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); in si_fan_ctrl_start_smc_fan_control()
6101 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) in si_fan_ctrl_stop_smc_fan_control() argument
6103 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_stop_smc_fan_control()
6106 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); in si_fan_ctrl_stop_smc_fan_control()
6116 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, in si_fan_ctrl_get_fan_speed_percent() argument
6122 if (rdev->pm.no_fan) in si_fan_ctrl_get_fan_speed_percent()
6141 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, in si_fan_ctrl_set_fan_speed_percent() argument
6144 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_set_fan_speed_percent()
6149 if (rdev->pm.no_fan) in si_fan_ctrl_set_fan_speed_percent()
6174 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) in si_fan_ctrl_set_mode() argument
6178 if (rdev->pm.dpm.fan.ucode_fan_control) in si_fan_ctrl_set_mode()
6179 si_fan_ctrl_stop_smc_fan_control(rdev); in si_fan_ctrl_set_mode()
6180 si_fan_ctrl_set_static_mode(rdev, mode); in si_fan_ctrl_set_mode()
6183 if (rdev->pm.dpm.fan.ucode_fan_control) in si_fan_ctrl_set_mode()
6184 si_thermal_start_smc_fan_control(rdev); in si_fan_ctrl_set_mode()
6186 si_fan_ctrl_set_default_mode(rdev); in si_fan_ctrl_set_mode()
6190 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) in si_fan_ctrl_get_mode() argument
6192 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_get_mode()
6203 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6207 u32 xclk = radeon_get_xclk(rdev);
6209 if (rdev->pm.no_fan)
6212 if (rdev->pm.fan_pulses_per_revolution == 0)
6224 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6228 u32 xclk = radeon_get_xclk(rdev);
6230 if (rdev->pm.no_fan)
6233 if (rdev->pm.fan_pulses_per_revolution == 0)
6236 if ((speed < rdev->pm.fan_min_rpm) ||
6237 (speed > rdev->pm.fan_max_rpm))
6240 if (rdev->pm.dpm.fan.ucode_fan_control)
6241 si_fan_ctrl_stop_smc_fan_control(rdev);
6248 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6254 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) in si_fan_ctrl_set_default_mode() argument
6256 struct si_power_info *si_pi = si_get_pi(rdev); in si_fan_ctrl_set_default_mode()
6271 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) in si_thermal_start_smc_fan_control() argument
6273 if (rdev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_smc_fan_control()
6274 si_fan_ctrl_start_smc_fan_control(rdev); in si_thermal_start_smc_fan_control()
6275 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); in si_thermal_start_smc_fan_control()
6279 static void si_thermal_initialize(struct radeon_device *rdev) in si_thermal_initialize() argument
6283 if (rdev->pm.fan_pulses_per_revolution) { in si_thermal_initialize()
6285 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); in si_thermal_initialize()
6294 static int si_thermal_start_thermal_controller(struct radeon_device *rdev) in si_thermal_start_thermal_controller() argument
6298 si_thermal_initialize(rdev); in si_thermal_start_thermal_controller()
6299 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); in si_thermal_start_thermal_controller()
6302 ret = si_thermal_enable_alert(rdev, true); in si_thermal_start_thermal_controller()
6305 if (rdev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_thermal_controller()
6306 ret = si_halt_smc(rdev); in si_thermal_start_thermal_controller()
6309 ret = si_thermal_setup_fan_table(rdev); in si_thermal_start_thermal_controller()
6312 ret = si_resume_smc(rdev); in si_thermal_start_thermal_controller()
6315 si_thermal_start_smc_fan_control(rdev); in si_thermal_start_thermal_controller()
6321 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) in si_thermal_stop_thermal_controller() argument
6323 if (!rdev->pm.no_fan) { in si_thermal_stop_thermal_controller()
6324 si_fan_ctrl_set_default_mode(rdev); in si_thermal_stop_thermal_controller()
6325 si_fan_ctrl_stop_smc_fan_control(rdev); in si_thermal_stop_thermal_controller()
6329 int si_dpm_enable(struct radeon_device *rdev) in si_dpm_enable() argument
6331 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_dpm_enable()
6332 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_enable()
6333 struct si_power_info *si_pi = si_get_pi(rdev); in si_dpm_enable()
6334 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in si_dpm_enable()
6337 if (si_is_smc_running(rdev)) in si_dpm_enable()
6340 si_enable_voltage_control(rdev, true); in si_dpm_enable()
6342 si_get_mvdd_configuration(rdev); in si_dpm_enable()
6344 ret = si_construct_voltage_tables(rdev); in si_dpm_enable()
6351 ret = si_initialize_mc_reg_table(rdev); in si_dpm_enable()
6356 si_enable_spread_spectrum(rdev, true); in si_dpm_enable()
6358 si_enable_thermal_protection(rdev, true); in si_dpm_enable()
6359 si_setup_bsp(rdev); in si_dpm_enable()
6360 si_program_git(rdev); in si_dpm_enable()
6361 si_program_tp(rdev); in si_dpm_enable()
6362 si_program_tpp(rdev); in si_dpm_enable()
6363 si_program_sstp(rdev); in si_dpm_enable()
6364 si_enable_display_gap(rdev); in si_dpm_enable()
6365 si_program_vc(rdev); in si_dpm_enable()
6366 ret = si_upload_firmware(rdev); in si_dpm_enable()
6371 ret = si_process_firmware_header(rdev); in si_dpm_enable()
6376 ret = si_initial_switch_from_arb_f0_to_f1(rdev); in si_dpm_enable()
6381 ret = si_init_smc_table(rdev); in si_dpm_enable()
6386 ret = si_init_smc_spll_table(rdev); in si_dpm_enable()
6391 ret = si_init_arb_table_index(rdev); in si_dpm_enable()
6397 ret = si_populate_mc_reg_table(rdev, boot_ps); in si_dpm_enable()
6403 ret = si_initialize_smc_cac_tables(rdev); in si_dpm_enable()
6408 ret = si_initialize_hardware_cac_manager(rdev); in si_dpm_enable()
6413 ret = si_initialize_smc_dte_tables(rdev); in si_dpm_enable()
6418 ret = si_populate_smc_tdp_limits(rdev, boot_ps); in si_dpm_enable()
6423 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); in si_dpm_enable()
6428 si_program_response_times(rdev); in si_dpm_enable()
6429 si_program_ds_registers(rdev); in si_dpm_enable()
6430 si_dpm_start_smc(rdev); in si_dpm_enable()
6431 ret = si_notify_smc_display_change(rdev, false); in si_dpm_enable()
6436 si_enable_sclk_control(rdev, true); in si_dpm_enable()
6437 si_start_dpm(rdev); in si_dpm_enable()
6439 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); in si_dpm_enable()
6441 si_thermal_start_thermal_controller(rdev); in si_dpm_enable()
6443 ni_update_current_ps(rdev, boot_ps); in si_dpm_enable()
6448 static int si_set_temperature_range(struct radeon_device *rdev) in si_set_temperature_range() argument
6452 ret = si_thermal_enable_alert(rdev, false); in si_set_temperature_range()
6455 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); in si_set_temperature_range()
6458 ret = si_thermal_enable_alert(rdev, true); in si_set_temperature_range()
6465 int si_dpm_late_enable(struct radeon_device *rdev) in si_dpm_late_enable() argument
6469 ret = si_set_temperature_range(rdev); in si_dpm_late_enable()
6476 void si_dpm_disable(struct radeon_device *rdev) in si_dpm_disable() argument
6478 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_dpm_disable()
6479 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in si_dpm_disable()
6481 if (!si_is_smc_running(rdev)) in si_dpm_disable()
6483 si_thermal_stop_thermal_controller(rdev); in si_dpm_disable()
6484 si_disable_ulv(rdev); in si_dpm_disable()
6485 si_clear_vc(rdev); in si_dpm_disable()
6487 si_enable_thermal_protection(rdev, false); in si_dpm_disable()
6488 si_enable_power_containment(rdev, boot_ps, false); in si_dpm_disable()
6489 si_enable_smc_cac(rdev, boot_ps, false); in si_dpm_disable()
6490 si_enable_spread_spectrum(rdev, false); in si_dpm_disable()
6491 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); in si_dpm_disable()
6492 si_stop_dpm(rdev); in si_dpm_disable()
6493 si_reset_to_default(rdev); in si_dpm_disable()
6494 si_dpm_stop_smc(rdev); in si_dpm_disable()
6495 si_force_switch_to_arb_f0(rdev); in si_dpm_disable()
6497 ni_update_current_ps(rdev, boot_ps); in si_dpm_disable()
6500 int si_dpm_pre_set_power_state(struct radeon_device *rdev) in si_dpm_pre_set_power_state() argument
6502 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_pre_set_power_state()
6503 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in si_dpm_pre_set_power_state()
6506 ni_update_requested_ps(rdev, new_ps); in si_dpm_pre_set_power_state()
6508 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); in si_dpm_pre_set_power_state()
6513 static int si_power_control_set_level(struct radeon_device *rdev) in si_power_control_set_level() argument
6515 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; in si_power_control_set_level()
6518 ret = si_restrict_performance_levels_before_switch(rdev); in si_power_control_set_level()
6521 ret = si_halt_smc(rdev); in si_power_control_set_level()
6524 ret = si_populate_smc_tdp_limits(rdev, new_ps); in si_power_control_set_level()
6527 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); in si_power_control_set_level()
6530 ret = si_resume_smc(rdev); in si_power_control_set_level()
6533 ret = si_set_sw_state(rdev); in si_power_control_set_level()
6539 int si_dpm_set_power_state(struct radeon_device *rdev) in si_dpm_set_power_state() argument
6541 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_set_power_state()
6546 ret = si_disable_ulv(rdev); in si_dpm_set_power_state()
6551 ret = si_restrict_performance_levels_before_switch(rdev); in si_dpm_set_power_state()
6557 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6558 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6559 ret = si_enable_power_containment(rdev, new_ps, false); in si_dpm_set_power_state()
6564 ret = si_enable_smc_cac(rdev, new_ps, false); in si_dpm_set_power_state()
6569 ret = si_halt_smc(rdev); in si_dpm_set_power_state()
6574 ret = si_upload_sw_state(rdev, new_ps); in si_dpm_set_power_state()
6579 ret = si_upload_smc_data(rdev); in si_dpm_set_power_state()
6584 ret = si_upload_ulv_state(rdev); in si_dpm_set_power_state()
6590 ret = si_upload_mc_reg_table(rdev, new_ps); in si_dpm_set_power_state()
6596 ret = si_program_memory_timing_parameters(rdev, new_ps); in si_dpm_set_power_state()
6601 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6603 ret = si_resume_smc(rdev); in si_dpm_set_power_state()
6608 ret = si_set_sw_state(rdev); in si_dpm_set_power_state()
6613 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6614 si_set_vce_clock(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6616 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6617 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); in si_dpm_set_power_state()
6622 ret = si_enable_smc_cac(rdev, new_ps, true); in si_dpm_set_power_state()
6627 ret = si_enable_power_containment(rdev, new_ps, true); in si_dpm_set_power_state()
6633 ret = si_power_control_set_level(rdev); in si_dpm_set_power_state()
6642 void si_dpm_post_set_power_state(struct radeon_device *rdev) in si_dpm_post_set_power_state() argument
6644 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_post_set_power_state()
6647 ni_update_current_ps(rdev, new_ps); in si_dpm_post_set_power_state()
6651 void si_dpm_reset_asic(struct radeon_device *rdev)
6653 si_restrict_performance_levels_before_switch(rdev);
6654 si_disable_ulv(rdev);
6655 si_set_boot_state(rdev);
6659 void si_dpm_display_configuration_changed(struct radeon_device *rdev) in si_dpm_display_configuration_changed() argument
6661 si_program_display_gap(rdev); in si_dpm_display_configuration_changed()
6686 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, in si_parse_pplib_non_clock_info() argument
6707 rdev->pm.dpm.boot_ps = rps; in si_parse_pplib_non_clock_info()
6709 rdev->pm.dpm.uvd_ps = rps; in si_parse_pplib_non_clock_info()
6712 static void si_parse_pplib_clock_info(struct radeon_device *rdev, in si_parse_pplib_clock_info() argument
6716 struct rv7xx_power_info *pi = rv770_get_pi(rdev); in si_parse_pplib_clock_info()
6717 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_parse_pplib_clock_info()
6718 struct si_power_info *si_pi = si_get_pi(rdev); in si_parse_pplib_clock_info()
6734 pl->pcie_gen = r600_get_pcie_gen_support(rdev, in si_parse_pplib_clock_info()
6740 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, in si_parse_pplib_clock_info()
6771 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); in si_parse_pplib_clock_info()
6772 pl->mclk = rdev->clock.default_mclk; in si_parse_pplib_clock_info()
6773 pl->sclk = rdev->clock.default_sclk; in si_parse_pplib_clock_info()
6781 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in si_parse_pplib_clock_info()
6782 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in si_parse_pplib_clock_info()
6783 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in si_parse_pplib_clock_info()
6784 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in si_parse_pplib_clock_info()
6788 static int si_parse_power_table(struct radeon_device *rdev) in si_parse_power_table() argument
6790 struct radeon_mode_info *mode_info = &rdev->mode_info; in si_parse_power_table()
6820 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in si_parse_power_table()
6823 if (!rdev->pm.dpm.ps) in si_parse_power_table()
6832 if (!rdev->pm.power_state[i].clock_info) in si_parse_power_table()
6836 kfree(rdev->pm.dpm.ps); in si_parse_power_table()
6839 rdev->pm.dpm.ps[i].ps_priv = ps; in si_parse_power_table()
6840 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in si_parse_power_table()
6854 si_parse_pplib_clock_info(rdev, in si_parse_power_table()
6855 &rdev->pm.dpm.ps[i], k, in si_parse_power_table()
6861 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in si_parse_power_table()
6866 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; in si_parse_power_table()
6873 rdev->pm.dpm.vce_states[i].sclk = sclk; in si_parse_power_table()
6874 rdev->pm.dpm.vce_states[i].mclk = mclk; in si_parse_power_table()
6880 int si_dpm_init(struct radeon_device *rdev) in si_dpm_init() argument
6888 struct pci_dev *root = rdev->pdev->bus->self; in si_dpm_init()
6894 rdev->pm.dpm.priv = si_pi; in si_dpm_init()
6899 if (!pci_is_root_bus(rdev->pdev->bus)) in si_dpm_init()
6915 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); in si_dpm_init()
6917 si_set_max_cu_value(rdev); in si_dpm_init()
6919 rv770_get_max_vddc(rdev); in si_dpm_init()
6920 si_get_leakage_vddc(rdev); in si_dpm_init()
6921 si_patch_dependency_tables_based_on_leakage(rdev); in si_dpm_init()
6928 ret = r600_get_platform_caps(rdev); in si_dpm_init()
6932 ret = r600_parse_extended_power_table(rdev); in si_dpm_init()
6936 ret = si_parse_power_table(rdev); in si_dpm_init()
6940 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in si_dpm_init()
6944 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in si_dpm_init()
6945 r600_free_extended_power_table(rdev); in si_dpm_init()
6948 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in si_dpm_init()
6949 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in si_dpm_init()
6950 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in si_dpm_init()
6951 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in si_dpm_init()
6952 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in si_dpm_init()
6953 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in si_dpm_init()
6954 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in si_dpm_init()
6955 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in si_dpm_init()
6956 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in si_dpm_init()
6958 if (rdev->pm.dpm.voltage_response_time == 0) in si_dpm_init()
6959 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; in si_dpm_init()
6960 if (rdev->pm.dpm.backbias_response_time == 0) in si_dpm_init()
6961 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; in si_dpm_init()
6963 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in si_dpm_init()
6973 if (si_is_special_1gb_platform(rdev)) in si_dpm_init()
6983 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in si_dpm_init()
6987 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in si_dpm_init()
6990 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in si_dpm_init()
6995 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, in si_dpm_init()
6999 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, in si_dpm_init()
7003 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, in si_dpm_init()
7007 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in si_dpm_init()
7010 rv770_get_engine_memory_ss(rdev); in si_dpm_init()
7021 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) in si_dpm_init()
7031 radeon_acpi_is_pcie_performance_request_supported(rdev); in si_dpm_init()
7038 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in si_dpm_init()
7039 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in si_dpm_init()
7040 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in si_dpm_init()
7041 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in si_dpm_init()
7042 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in si_dpm_init()
7043 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in si_dpm_init()
7044 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in si_dpm_init()
7046 si_initialize_powertune_defaults(rdev); in si_dpm_init()
7049 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in si_dpm_init()
7050 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()
7051 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in si_dpm_init()
7052 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_dpm_init()
7059 void si_dpm_fini(struct radeon_device *rdev) in si_dpm_fini() argument
7063 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in si_dpm_fini()
7064 kfree(rdev->pm.dpm.ps[i].ps_priv); in si_dpm_fini()
7066 kfree(rdev->pm.dpm.ps); in si_dpm_fini()
7067 kfree(rdev->pm.dpm.priv); in si_dpm_fini()
7068 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in si_dpm_fini()
7069 r600_free_extended_power_table(rdev); in si_dpm_fini()
7072 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, in si_dpm_debugfs_print_current_performance_level() argument
7075 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_debugfs_print_current_performance_level()
7093 u32 si_dpm_get_current_sclk(struct radeon_device *rdev) in si_dpm_get_current_sclk() argument
7095 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_get_current_sclk()
7111 u32 si_dpm_get_current_mclk(struct radeon_device *rdev) in si_dpm_get_current_mclk() argument
7113 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); in si_dpm_get_current_mclk()