Lines Matching refs:rdev
49 static void rv770_gpu_init(struct radeon_device *rdev);
50 void rv770_fini(struct radeon_device *rdev);
51 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
52 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
54 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in rv770_set_uvd_clocks() argument
60 if (rdev->family == CHIP_RV740) in rv770_set_uvd_clocks()
61 return evergreen_set_uvd_clocks(rdev, vclk, dclk); in rv770_set_uvd_clocks()
74 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in rv770_set_uvd_clocks()
94 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in rv770_set_uvd_clocks()
125 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in rv770_set_uvd_clocks()
712 static void rv770_init_golden_registers(struct radeon_device *rdev) in rv770_init_golden_registers() argument
714 switch (rdev->family) { in rv770_init_golden_registers()
716 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
719 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
722 if (rdev->pdev->device == 0x994e) in rv770_init_golden_registers()
723 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
727 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
730 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
735 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
738 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
741 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
744 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
749 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
752 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
755 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
758 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
763 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
766 radeon_program_register_sequence(rdev, in rv770_init_golden_registers()
786 u32 rv770_get_xclk(struct radeon_device *rdev) in rv770_get_xclk() argument
788 u32 reference_clock = rdev->clock.spll.reference_freq; in rv770_get_xclk()
800 void rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) in rv770_page_flip() argument
802 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rv770_page_flip()
831 for (i = 0; i < rdev->usec_timeout; i++) { in rv770_page_flip()
843 bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc_id) in rv770_page_flip_pending() argument
845 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rv770_page_flip_pending()
853 int rv770_get_temp(struct radeon_device *rdev) in rv770_get_temp() argument
872 void rv770_pm_misc(struct radeon_device *rdev) in rv770_pm_misc() argument
874 int req_ps_idx = rdev->pm.requested_power_state_index; in rv770_pm_misc()
875 int req_cm_idx = rdev->pm.requested_clock_mode_index; in rv770_pm_misc()
876 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; in rv770_pm_misc()
883 if (voltage->voltage != rdev->pm.current_vddc) { in rv770_pm_misc()
884 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); in rv770_pm_misc()
885 rdev->pm.current_vddc = voltage->voltage; in rv770_pm_misc()
894 static int rv770_pcie_gart_enable(struct radeon_device *rdev) in rv770_pcie_gart_enable() argument
899 if (rdev->gart.robj == NULL) { in rv770_pcie_gart_enable()
900 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in rv770_pcie_gart_enable()
903 r = radeon_gart_table_vram_pin(rdev); in rv770_pcie_gart_enable()
920 if (rdev->family == CHIP_RV740) in rv770_pcie_gart_enable()
926 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in rv770_pcie_gart_enable()
927 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in rv770_pcie_gart_enable()
928 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in rv770_pcie_gart_enable()
932 (u32)(rdev->dummy_page.addr >> 12)); in rv770_pcie_gart_enable()
936 r600_pcie_gart_tlb_flush(rdev); in rv770_pcie_gart_enable()
938 (unsigned)(rdev->mc.gtt_size >> 20), in rv770_pcie_gart_enable()
939 (unsigned long long)rdev->gart.table_addr); in rv770_pcie_gart_enable()
940 rdev->gart.ready = true; in rv770_pcie_gart_enable()
944 static void rv770_pcie_gart_disable(struct radeon_device *rdev) in rv770_pcie_gart_disable() argument
967 radeon_gart_table_vram_unpin(rdev); in rv770_pcie_gart_disable()
970 static void rv770_pcie_gart_fini(struct radeon_device *rdev) in rv770_pcie_gart_fini() argument
972 radeon_gart_fini(rdev); in rv770_pcie_gart_fini()
973 rv770_pcie_gart_disable(rdev); in rv770_pcie_gart_fini()
974 radeon_gart_table_vram_free(rdev); in rv770_pcie_gart_fini()
978 static void rv770_agp_enable(struct radeon_device *rdev) in rv770_agp_enable() argument
1005 static void rv770_mc_program(struct radeon_device *rdev) in rv770_mc_program() argument
1024 rv515_mc_stop(rdev, &save); in rv770_mc_program()
1025 if (r600_mc_wait_for_idle(rdev)) { in rv770_mc_program()
1026 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in rv770_mc_program()
1031 if (rdev->flags & RADEON_IS_AGP) { in rv770_mc_program()
1032 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in rv770_mc_program()
1035 rdev->mc.vram_start >> 12); in rv770_mc_program()
1037 rdev->mc.gtt_end >> 12); in rv770_mc_program()
1041 rdev->mc.gtt_start >> 12); in rv770_mc_program()
1043 rdev->mc.vram_end >> 12); in rv770_mc_program()
1047 rdev->mc.vram_start >> 12); in rv770_mc_program()
1049 rdev->mc.vram_end >> 12); in rv770_mc_program()
1051 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in rv770_mc_program()
1052 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in rv770_mc_program()
1053 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in rv770_mc_program()
1055 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in rv770_mc_program()
1058 if (rdev->flags & RADEON_IS_AGP) { in rv770_mc_program()
1059 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); in rv770_mc_program()
1060 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); in rv770_mc_program()
1061 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in rv770_mc_program()
1067 if (r600_mc_wait_for_idle(rdev)) { in rv770_mc_program()
1068 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in rv770_mc_program()
1070 rv515_mc_resume(rdev, &save); in rv770_mc_program()
1073 rv515_vga_render_disable(rdev); in rv770_mc_program()
1080 void r700_cp_stop(struct radeon_device *rdev) in r700_cp_stop() argument
1082 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in r700_cp_stop()
1083 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r700_cp_stop()
1086 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r700_cp_stop()
1089 static int rv770_cp_load_microcode(struct radeon_device *rdev) in rv770_cp_load_microcode() argument
1094 if (!rdev->me_fw || !rdev->pfp_fw) in rv770_cp_load_microcode()
1097 r700_cp_stop(rdev); in rv770_cp_load_microcode()
1110 fw_data = (const __be32 *)rdev->pfp_fw->data; in rv770_cp_load_microcode()
1116 fw_data = (const __be32 *)rdev->me_fw->data; in rv770_cp_load_microcode()
1127 void r700_cp_fini(struct radeon_device *rdev) in r700_cp_fini() argument
1129 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r700_cp_fini()
1130 r700_cp_stop(rdev); in r700_cp_fini()
1131 radeon_ring_fini(rdev, ring); in r700_cp_fini()
1132 radeon_scratch_free(rdev, ring->rptr_save_reg); in r700_cp_fini()
1135 void rv770_set_clk_bypass_mode(struct radeon_device *rdev) in rv770_set_clk_bypass_mode() argument
1139 if (rdev->flags & RADEON_IS_IGP) in rv770_set_clk_bypass_mode()
1147 for (i = 0; i < rdev->usec_timeout; i++) { in rv770_set_clk_bypass_mode()
1157 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730)) in rv770_set_clk_bypass_mode()
1167 static void rv770_gpu_init(struct radeon_device *rdev) in rv770_gpu_init() argument
1191 rdev->config.rv770.tiling_group_size = 256; in rv770_gpu_init()
1192 switch (rdev->family) { in rv770_gpu_init()
1194 rdev->config.rv770.max_pipes = 4; in rv770_gpu_init()
1195 rdev->config.rv770.max_tile_pipes = 8; in rv770_gpu_init()
1196 rdev->config.rv770.max_simds = 10; in rv770_gpu_init()
1197 rdev->config.rv770.max_backends = 4; in rv770_gpu_init()
1198 rdev->config.rv770.max_gprs = 256; in rv770_gpu_init()
1199 rdev->config.rv770.max_threads = 248; in rv770_gpu_init()
1200 rdev->config.rv770.max_stack_entries = 512; in rv770_gpu_init()
1201 rdev->config.rv770.max_hw_contexts = 8; in rv770_gpu_init()
1202 rdev->config.rv770.max_gs_threads = 16 * 2; in rv770_gpu_init()
1203 rdev->config.rv770.sx_max_export_size = 128; in rv770_gpu_init()
1204 rdev->config.rv770.sx_max_export_pos_size = 16; in rv770_gpu_init()
1205 rdev->config.rv770.sx_max_export_smx_size = 112; in rv770_gpu_init()
1206 rdev->config.rv770.sq_num_cf_insts = 2; in rv770_gpu_init()
1208 rdev->config.rv770.sx_num_of_sets = 7; in rv770_gpu_init()
1209 rdev->config.rv770.sc_prim_fifo_size = 0xF9; in rv770_gpu_init()
1210 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; in rv770_gpu_init()
1211 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; in rv770_gpu_init()
1214 rdev->config.rv770.max_pipes = 2; in rv770_gpu_init()
1215 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()
1216 rdev->config.rv770.max_simds = 8; in rv770_gpu_init()
1217 rdev->config.rv770.max_backends = 2; in rv770_gpu_init()
1218 rdev->config.rv770.max_gprs = 128; in rv770_gpu_init()
1219 rdev->config.rv770.max_threads = 248; in rv770_gpu_init()
1220 rdev->config.rv770.max_stack_entries = 256; in rv770_gpu_init()
1221 rdev->config.rv770.max_hw_contexts = 8; in rv770_gpu_init()
1222 rdev->config.rv770.max_gs_threads = 16 * 2; in rv770_gpu_init()
1223 rdev->config.rv770.sx_max_export_size = 256; in rv770_gpu_init()
1224 rdev->config.rv770.sx_max_export_pos_size = 32; in rv770_gpu_init()
1225 rdev->config.rv770.sx_max_export_smx_size = 224; in rv770_gpu_init()
1226 rdev->config.rv770.sq_num_cf_insts = 2; in rv770_gpu_init()
1228 rdev->config.rv770.sx_num_of_sets = 7; in rv770_gpu_init()
1229 rdev->config.rv770.sc_prim_fifo_size = 0xf9; in rv770_gpu_init()
1230 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; in rv770_gpu_init()
1231 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; in rv770_gpu_init()
1232 if (rdev->config.rv770.sx_max_export_pos_size > 16) { in rv770_gpu_init()
1233 rdev->config.rv770.sx_max_export_pos_size -= 16; in rv770_gpu_init()
1234 rdev->config.rv770.sx_max_export_smx_size += 16; in rv770_gpu_init()
1238 rdev->config.rv770.max_pipes = 2; in rv770_gpu_init()
1239 rdev->config.rv770.max_tile_pipes = 2; in rv770_gpu_init()
1240 rdev->config.rv770.max_simds = 2; in rv770_gpu_init()
1241 rdev->config.rv770.max_backends = 1; in rv770_gpu_init()
1242 rdev->config.rv770.max_gprs = 256; in rv770_gpu_init()
1243 rdev->config.rv770.max_threads = 192; in rv770_gpu_init()
1244 rdev->config.rv770.max_stack_entries = 256; in rv770_gpu_init()
1245 rdev->config.rv770.max_hw_contexts = 4; in rv770_gpu_init()
1246 rdev->config.rv770.max_gs_threads = 8 * 2; in rv770_gpu_init()
1247 rdev->config.rv770.sx_max_export_size = 128; in rv770_gpu_init()
1248 rdev->config.rv770.sx_max_export_pos_size = 16; in rv770_gpu_init()
1249 rdev->config.rv770.sx_max_export_smx_size = 112; in rv770_gpu_init()
1250 rdev->config.rv770.sq_num_cf_insts = 1; in rv770_gpu_init()
1252 rdev->config.rv770.sx_num_of_sets = 7; in rv770_gpu_init()
1253 rdev->config.rv770.sc_prim_fifo_size = 0x40; in rv770_gpu_init()
1254 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; in rv770_gpu_init()
1255 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; in rv770_gpu_init()
1258 rdev->config.rv770.max_pipes = 4; in rv770_gpu_init()
1259 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()
1260 rdev->config.rv770.max_simds = 8; in rv770_gpu_init()
1261 rdev->config.rv770.max_backends = 4; in rv770_gpu_init()
1262 rdev->config.rv770.max_gprs = 256; in rv770_gpu_init()
1263 rdev->config.rv770.max_threads = 248; in rv770_gpu_init()
1264 rdev->config.rv770.max_stack_entries = 512; in rv770_gpu_init()
1265 rdev->config.rv770.max_hw_contexts = 8; in rv770_gpu_init()
1266 rdev->config.rv770.max_gs_threads = 16 * 2; in rv770_gpu_init()
1267 rdev->config.rv770.sx_max_export_size = 256; in rv770_gpu_init()
1268 rdev->config.rv770.sx_max_export_pos_size = 32; in rv770_gpu_init()
1269 rdev->config.rv770.sx_max_export_smx_size = 224; in rv770_gpu_init()
1270 rdev->config.rv770.sq_num_cf_insts = 2; in rv770_gpu_init()
1272 rdev->config.rv770.sx_num_of_sets = 7; in rv770_gpu_init()
1273 rdev->config.rv770.sc_prim_fifo_size = 0x100; in rv770_gpu_init()
1274 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; in rv770_gpu_init()
1275 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; in rv770_gpu_init()
1277 if (rdev->config.rv770.sx_max_export_pos_size > 16) { in rv770_gpu_init()
1278 rdev->config.rv770.sx_max_export_pos_size -= 16; in rv770_gpu_init()
1279 rdev->config.rv770.sx_max_export_smx_size += 16; in rv770_gpu_init()
1317 tmp = rdev->config.rv770.max_simds - in rv770_gpu_init()
1319 rdev->config.rv770.active_simds = tmp; in rv770_gpu_init()
1321 switch (rdev->config.rv770.max_tile_pipes) { in rv770_gpu_init()
1336 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; in rv770_gpu_init()
1340 for (i = 0; i < rdev->config.rv770.max_backends; i++) in rv770_gpu_init()
1344 for (i = 0; i < rdev->config.rv770.max_backends; i++) in rv770_gpu_init()
1348 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends, in rv770_gpu_init()
1351 rdev->config.rv770.backend_map = tmp; in rv770_gpu_init()
1353 if (rdev->family == CHIP_RV770) in rv770_gpu_init()
1361 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); in rv770_gpu_init()
1374 rdev->config.rv770.tile_config = gb_tiling_config; in rv770_gpu_init()
1381 if (rdev->family == CHIP_RV730) { in rv770_gpu_init()
1412 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); in rv770_gpu_init()
1415 if (rdev->family != CHIP_RV740) in rv770_gpu_init()
1421 if (rdev->family != CHIP_RV770) in rv770_gpu_init()
1426 switch (rdev->family) { in rv770_gpu_init()
1439 if (rdev->family != CHIP_RV770) { in rv770_gpu_init()
1445 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1)… in rv770_gpu_init()
1446 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | in rv770_gpu_init()
1447 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); in rv770_gpu_init()
1449 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | in rv770_gpu_init()
1450 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | in rv770_gpu_init()
1451 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); in rv770_gpu_init()
1461 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | in rv770_gpu_init()
1464 switch (rdev->family) { in rv770_gpu_init()
1492 if (rdev->family == CHIP_RV710) in rv770_gpu_init()
1498 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | in rv770_gpu_init()
1499 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | in rv770_gpu_init()
1500 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); in rv770_gpu_init()
1502 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | in rv770_gpu_init()
1503 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); in rv770_gpu_init()
1505 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | in rv770_gpu_init()
1506 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | in rv770_gpu_init()
1507 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); in rv770_gpu_init()
1508 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) in rv770_gpu_init()
1509 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); in rv770_gpu_init()
1511 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); in rv770_gpu_init()
1514 …WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/… in rv770_gpu_init()
1515 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); in rv770_gpu_init()
1517 …WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/… in rv770_gpu_init()
1518 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); in rv770_gpu_init()
1520 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | in rv770_gpu_init()
1521 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | in rv770_gpu_init()
1522 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | in rv770_gpu_init()
1523 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); in rv770_gpu_init()
1537 if (rdev->family == CHIP_RV710) in rv770_gpu_init()
1544 switch (rdev->family) { in rv770_gpu_init()
1557 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; in rv770_gpu_init()
1603 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) in r700_vram_gtt_location() argument
1609 dev_warn(rdev->dev, "limiting VRAM\n"); in r700_vram_gtt_location()
1613 if (rdev->flags & RADEON_IS_AGP) { in r700_vram_gtt_location()
1618 dev_warn(rdev->dev, "limiting VRAM\n"); in r700_vram_gtt_location()
1625 dev_warn(rdev->dev, "limiting VRAM\n"); in r700_vram_gtt_location()
1632 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", in r700_vram_gtt_location()
1636 radeon_vram_location(rdev, &rdev->mc, 0); in r700_vram_gtt_location()
1637 rdev->mc.gtt_base_align = 0; in r700_vram_gtt_location()
1638 radeon_gtt_location(rdev, mc); in r700_vram_gtt_location()
1642 static int rv770_mc_init(struct radeon_device *rdev) in rv770_mc_init() argument
1648 rdev->mc.vram_is_ddr = true; in rv770_mc_init()
1673 rdev->mc.vram_width = numchan * chansize; in rv770_mc_init()
1675 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in rv770_mc_init()
1676 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in rv770_mc_init()
1678 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in rv770_mc_init()
1679 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in rv770_mc_init()
1680 rdev->mc.visible_vram_size = rdev->mc.aper_size; in rv770_mc_init()
1681 r700_vram_gtt_location(rdev, &rdev->mc); in rv770_mc_init()
1682 radeon_update_bandwidth_info(rdev); in rv770_mc_init()
1687 static void rv770_uvd_init(struct radeon_device *rdev) in rv770_uvd_init() argument
1691 if (!rdev->has_uvd) in rv770_uvd_init()
1694 r = radeon_uvd_init(rdev); in rv770_uvd_init()
1696 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); in rv770_uvd_init()
1703 rdev->has_uvd = false; in rv770_uvd_init()
1706 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in rv770_uvd_init()
1707 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in rv770_uvd_init()
1710 static void rv770_uvd_start(struct radeon_device *rdev) in rv770_uvd_start() argument
1714 if (!rdev->has_uvd) in rv770_uvd_start()
1717 r = uvd_v2_2_resume(rdev); in rv770_uvd_start()
1719 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); in rv770_uvd_start()
1722 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); in rv770_uvd_start()
1724 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); in rv770_uvd_start()
1730 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in rv770_uvd_start()
1733 static void rv770_uvd_resume(struct radeon_device *rdev) in rv770_uvd_resume() argument
1738 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) in rv770_uvd_resume()
1741 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in rv770_uvd_resume()
1742 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); in rv770_uvd_resume()
1744 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); in rv770_uvd_resume()
1747 r = uvd_v1_0_init(rdev); in rv770_uvd_resume()
1749 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); in rv770_uvd_resume()
1754 static int rv770_startup(struct radeon_device *rdev) in rv770_startup() argument
1760 rv770_pcie_gen2_enable(rdev); in rv770_startup()
1763 r = r600_vram_scratch_init(rdev); in rv770_startup()
1767 rv770_mc_program(rdev); in rv770_startup()
1769 if (rdev->flags & RADEON_IS_AGP) { in rv770_startup()
1770 rv770_agp_enable(rdev); in rv770_startup()
1772 r = rv770_pcie_gart_enable(rdev); in rv770_startup()
1777 rv770_gpu_init(rdev); in rv770_startup()
1780 r = radeon_wb_init(rdev); in rv770_startup()
1784 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in rv770_startup()
1786 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in rv770_startup()
1790 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); in rv770_startup()
1792 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in rv770_startup()
1796 rv770_uvd_start(rdev); in rv770_startup()
1799 if (!rdev->irq.installed) { in rv770_startup()
1800 r = radeon_irq_kms_init(rdev); in rv770_startup()
1805 r = r600_irq_init(rdev); in rv770_startup()
1808 radeon_irq_kms_fini(rdev); in rv770_startup()
1811 r600_irq_set(rdev); in rv770_startup()
1813 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in rv770_startup()
1814 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in rv770_startup()
1819 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in rv770_startup()
1820 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in rv770_startup()
1825 r = rv770_cp_load_microcode(rdev); in rv770_startup()
1828 r = r600_cp_resume(rdev); in rv770_startup()
1832 r = r600_dma_resume(rdev); in rv770_startup()
1836 rv770_uvd_resume(rdev); in rv770_startup()
1838 r = radeon_ib_pool_init(rdev); in rv770_startup()
1840 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in rv770_startup()
1844 r = radeon_audio_init(rdev); in rv770_startup()
1853 int rv770_resume(struct radeon_device *rdev) in rv770_resume() argument
1862 atom_asic_init(rdev->mode_info.atom_context); in rv770_resume()
1865 rv770_init_golden_registers(rdev); in rv770_resume()
1867 if (rdev->pm.pm_method == PM_METHOD_DPM) in rv770_resume()
1868 radeon_pm_resume(rdev); in rv770_resume()
1870 rdev->accel_working = true; in rv770_resume()
1871 r = rv770_startup(rdev); in rv770_resume()
1874 rdev->accel_working = false; in rv770_resume()
1882 int rv770_suspend(struct radeon_device *rdev) in rv770_suspend() argument
1884 radeon_pm_suspend(rdev); in rv770_suspend()
1885 radeon_audio_fini(rdev); in rv770_suspend()
1886 if (rdev->has_uvd) { in rv770_suspend()
1887 radeon_uvd_suspend(rdev); in rv770_suspend()
1888 uvd_v1_0_fini(rdev); in rv770_suspend()
1890 r700_cp_stop(rdev); in rv770_suspend()
1891 r600_dma_stop(rdev); in rv770_suspend()
1892 r600_irq_suspend(rdev); in rv770_suspend()
1893 radeon_wb_disable(rdev); in rv770_suspend()
1894 rv770_pcie_gart_disable(rdev); in rv770_suspend()
1905 int rv770_init(struct radeon_device *rdev) in rv770_init() argument
1910 if (!radeon_get_bios(rdev)) { in rv770_init()
1911 if (ASIC_IS_AVIVO(rdev)) in rv770_init()
1915 if (!rdev->is_atom_bios) { in rv770_init()
1916 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); in rv770_init()
1919 r = radeon_atombios_init(rdev); in rv770_init()
1923 if (!radeon_card_posted(rdev)) { in rv770_init()
1924 if (!rdev->bios) { in rv770_init()
1925 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in rv770_init()
1929 atom_asic_init(rdev->mode_info.atom_context); in rv770_init()
1932 rv770_init_golden_registers(rdev); in rv770_init()
1934 r600_scratch_init(rdev); in rv770_init()
1936 radeon_surface_init(rdev); in rv770_init()
1938 radeon_get_clock_info(rdev->ddev); in rv770_init()
1940 radeon_fence_driver_init(rdev); in rv770_init()
1942 if (rdev->flags & RADEON_IS_AGP) { in rv770_init()
1943 r = radeon_agp_init(rdev); in rv770_init()
1945 radeon_agp_disable(rdev); in rv770_init()
1947 r = rv770_mc_init(rdev); in rv770_init()
1951 r = radeon_bo_init(rdev); in rv770_init()
1955 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in rv770_init()
1956 r = r600_init_microcode(rdev); in rv770_init()
1964 radeon_pm_init(rdev); in rv770_init()
1966 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; in rv770_init()
1967 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); in rv770_init()
1969 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; in rv770_init()
1970 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); in rv770_init()
1972 rv770_uvd_init(rdev); in rv770_init()
1974 rdev->ih.ring_obj = NULL; in rv770_init()
1975 r600_ih_ring_init(rdev, 64 * 1024); in rv770_init()
1977 r = r600_pcie_gart_init(rdev); in rv770_init()
1981 rdev->accel_working = true; in rv770_init()
1982 r = rv770_startup(rdev); in rv770_init()
1984 dev_err(rdev->dev, "disabling GPU acceleration\n"); in rv770_init()
1985 r700_cp_fini(rdev); in rv770_init()
1986 r600_dma_fini(rdev); in rv770_init()
1987 r600_irq_fini(rdev); in rv770_init()
1988 radeon_wb_fini(rdev); in rv770_init()
1989 radeon_ib_pool_fini(rdev); in rv770_init()
1990 radeon_irq_kms_fini(rdev); in rv770_init()
1991 rv770_pcie_gart_fini(rdev); in rv770_init()
1992 rdev->accel_working = false; in rv770_init()
1998 void rv770_fini(struct radeon_device *rdev) in rv770_fini() argument
2000 radeon_pm_fini(rdev); in rv770_fini()
2001 r700_cp_fini(rdev); in rv770_fini()
2002 r600_dma_fini(rdev); in rv770_fini()
2003 r600_irq_fini(rdev); in rv770_fini()
2004 radeon_wb_fini(rdev); in rv770_fini()
2005 radeon_ib_pool_fini(rdev); in rv770_fini()
2006 radeon_irq_kms_fini(rdev); in rv770_fini()
2007 uvd_v1_0_fini(rdev); in rv770_fini()
2008 radeon_uvd_fini(rdev); in rv770_fini()
2009 rv770_pcie_gart_fini(rdev); in rv770_fini()
2010 r600_vram_scratch_fini(rdev); in rv770_fini()
2011 radeon_gem_fini(rdev); in rv770_fini()
2012 radeon_fence_driver_fini(rdev); in rv770_fini()
2013 radeon_agp_fini(rdev); in rv770_fini()
2014 radeon_bo_fini(rdev); in rv770_fini()
2015 radeon_atombios_fini(rdev); in rv770_fini()
2016 kfree(rdev->bios); in rv770_fini()
2017 rdev->bios = NULL; in rv770_fini()
2020 static void rv770_pcie_gen2_enable(struct radeon_device *rdev) in rv770_pcie_gen2_enable() argument
2028 if (rdev->flags & RADEON_IS_IGP) in rv770_pcie_gen2_enable()
2031 if (!(rdev->flags & RADEON_IS_PCIE)) in rv770_pcie_gen2_enable()
2035 if (ASIC_IS_X2(rdev)) in rv770_pcie_gen2_enable()
2038 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && in rv770_pcie_gen2_enable()
2039 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) in rv770_pcie_gen2_enable()