112 				WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |  in pre_xfer()
115 				WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |  in pre_xfer()
126 		WREG32(rec->mask_clk_reg, temp);  in pre_xfer()
131 	WREG32(rec->a_clk_reg, temp);  in pre_xfer()
134 	WREG32(rec->a_data_reg, temp);  in pre_xfer()
138 	WREG32(rec->en_clk_reg, temp);  in pre_xfer()
141 	WREG32(rec->en_data_reg, temp);  in pre_xfer()
145 	WREG32(rec->mask_clk_reg, temp);  in pre_xfer()
149 	WREG32(rec->mask_data_reg, temp);  in pre_xfer()
164 	WREG32(rec->mask_clk_reg, temp);  in post_xfer()
168 	WREG32(rec->mask_data_reg, temp);  in post_xfer()
213 	WREG32(rec->en_clk_reg, val);  in set_clock()
226 	WREG32(rec->en_data_reg, val);  in set_data()
347 		WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);  in r100_hw_i2c_xfer()
461 		WREG32(i2c_cntl_0, (RADEON_I2C_DONE |  in r100_hw_i2c_xfer()
465 		WREG32(i2c_data, (p->addr << 1) & 0xff);  in r100_hw_i2c_xfer()
466 		WREG32(i2c_data, 0);  in r100_hw_i2c_xfer()
467 		WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |  in r100_hw_i2c_xfer()
471 		WREG32(i2c_cntl_0, reg);  in r100_hw_i2c_xfer()
482 				WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);  in r100_hw_i2c_xfer()
494 				WREG32(i2c_cntl_0, (RADEON_I2C_DONE |  in r100_hw_i2c_xfer()
498 				WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);  in r100_hw_i2c_xfer()
499 				WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |  in r100_hw_i2c_xfer()
503 				WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);  in r100_hw_i2c_xfer()
514 						WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);  in r100_hw_i2c_xfer()
521 				WREG32(i2c_cntl_0, (RADEON_I2C_DONE |  in r100_hw_i2c_xfer()
525 				WREG32(i2c_data, (p->addr << 1) & 0xff);  in r100_hw_i2c_xfer()
526 				WREG32(i2c_data, p->buf[j]);  in r100_hw_i2c_xfer()
527 				WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |  in r100_hw_i2c_xfer()
531 				WREG32(i2c_cntl_0, reg);  in r100_hw_i2c_xfer()
542 						WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);  in r100_hw_i2c_xfer()
552 	WREG32(i2c_cntl_0, 0);  in r100_hw_i2c_xfer()
553 	WREG32(i2c_cntl_1, 0);  in r100_hw_i2c_xfer()
554 	WREG32(i2c_cntl_0, (RADEON_I2C_DONE |  in r100_hw_i2c_xfer()
562 		WREG32(RADEON_BIOS_6_SCRATCH, tmp);  in r100_hw_i2c_xfer()
595 	WREG32(rec->mask_clk_reg, tmp);  in r500_hw_i2c_xfer()
600 	WREG32(rec->mask_data_reg, tmp);  in r500_hw_i2c_xfer()
606 	WREG32(rec->a_clk_reg, tmp);  in r500_hw_i2c_xfer()
611 	WREG32(rec->a_data_reg, tmp);  in r500_hw_i2c_xfer()
617 	WREG32(rec->en_clk_reg, tmp);  in r500_hw_i2c_xfer()
622 	WREG32(rec->en_data_reg, tmp);  in r500_hw_i2c_xfer()
627 	WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);  in r500_hw_i2c_xfer()
630 	WREG32(0x494, saved2 | 0x1);  in r500_hw_i2c_xfer()
632 	WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);  in r500_hw_i2c_xfer()
664 		WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |  in r500_hw_i2c_xfer()
667 		WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);  in r500_hw_i2c_xfer()
669 		WREG32(AVIVO_DC_I2C_RESET, 0);  in r500_hw_i2c_xfer()
671 		WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);  in r500_hw_i2c_xfer()
672 		WREG32(AVIVO_DC_I2C_DATA, 0);  in r500_hw_i2c_xfer()
674 		WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));  in r500_hw_i2c_xfer()
675 		WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |  in r500_hw_i2c_xfer()
678 		WREG32(AVIVO_DC_I2C_CONTROL1, reg);  in r500_hw_i2c_xfer()
679 		WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);  in r500_hw_i2c_xfer()
690 				WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);  in r500_hw_i2c_xfer()
708 				WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |  in r500_hw_i2c_xfer()
711 				WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);  in r500_hw_i2c_xfer()
713 				WREG32(AVIVO_DC_I2C_RESET, 0);  in r500_hw_i2c_xfer()
715 				WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);  in r500_hw_i2c_xfer()
716 				WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));  in r500_hw_i2c_xfer()
717 				WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |  in r500_hw_i2c_xfer()
720 				WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);  in r500_hw_i2c_xfer()
721 				WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);  in r500_hw_i2c_xfer()
732 						WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);  in r500_hw_i2c_xfer()
748 				WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |  in r500_hw_i2c_xfer()
751 				WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);  in r500_hw_i2c_xfer()
753 				WREG32(AVIVO_DC_I2C_RESET, 0);  in r500_hw_i2c_xfer()
755 				WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);  in r500_hw_i2c_xfer()
757 					WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);  in r500_hw_i2c_xfer()
759 				WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));  in r500_hw_i2c_xfer()
760 				WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |  in r500_hw_i2c_xfer()
763 				WREG32(AVIVO_DC_I2C_CONTROL1, reg);  in r500_hw_i2c_xfer()
764 				WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);  in r500_hw_i2c_xfer()
775 						WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);  in r500_hw_i2c_xfer()
787 	WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |  in r500_hw_i2c_xfer()
790 	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);  in r500_hw_i2c_xfer()
792 	WREG32(AVIVO_DC_I2C_RESET, 0);  in r500_hw_i2c_xfer()
794 	WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);  in r500_hw_i2c_xfer()
795 	WREG32(AVIVO_DC_I2C_CONTROL1, saved1);  in r500_hw_i2c_xfer()
796 	WREG32(0x494, saved2);  in r500_hw_i2c_xfer()
799 	WREG32(RADEON_BIOS_6_SCRATCH, tmp);  in r500_hw_i2c_xfer()