58 	WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);  in avivo_crtc_load_lut()
60 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);  in avivo_crtc_load_lut()
61 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);  in avivo_crtc_load_lut()
62 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);  in avivo_crtc_load_lut()
64 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);  in avivo_crtc_load_lut()
65 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);  in avivo_crtc_load_lut()
66 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);  in avivo_crtc_load_lut()
84 	WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);  in avivo_crtc_load_lut()
96 	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
98 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
99 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
100 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
102 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);  in dce4_crtc_load_lut()
103 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);  in dce4_crtc_load_lut()
104 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);  in dce4_crtc_load_lut()
106 	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
107 	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);  in dce4_crtc_load_lut()
109 	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
114 		WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,  in dce4_crtc_load_lut()
133 	WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
136 	WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
138 	WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
140 	WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
144 	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
146 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
147 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
148 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
150 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);  in dce5_crtc_load_lut()
151 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);  in dce5_crtc_load_lut()
152 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);  in dce5_crtc_load_lut()
154 	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
155 	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);  in dce5_crtc_load_lut()
157 	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
162 		WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
168 	WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
173 	WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
176 	WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
179 	WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
183 	WREG32(0x6940 + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
188 		WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()