Lines Matching +full:- +full:35000
42 struct radeon_pll *spll = &rdev->clock.spll; in radeon_legacy_get_engine_clock()
48 fb_div *= spll->reference_freq; in radeon_legacy_get_engine_clock()
72 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_legacy_get_memory_clock()
78 fb_div *= mpll->reference_freq; in radeon_legacy_get_memory_clock()
106 struct radeon_device *rdev = dev->dev_private; in radeon_read_clocks_OF()
107 struct device_node *dp = rdev->pdev->dev.of_node; in radeon_read_clocks_OF()
109 struct radeon_pll *p1pll = &rdev->clock.p1pll; in radeon_read_clocks_OF()
110 struct radeon_pll *p2pll = &rdev->clock.p2pll; in radeon_read_clocks_OF()
111 struct radeon_pll *spll = &rdev->clock.spll; in radeon_read_clocks_OF()
112 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_read_clocks_OF()
121 p1pll->reference_freq = p2pll->reference_freq = (*val) / 10; in radeon_read_clocks_OF()
122 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; in radeon_read_clocks_OF()
123 if (p1pll->reference_div < 2) in radeon_read_clocks_OF()
124 p1pll->reference_div = 12; in radeon_read_clocks_OF()
125 p2pll->reference_div = p1pll->reference_div; in radeon_read_clocks_OF()
127 /* These aren't in the device-tree */ in radeon_read_clocks_OF()
128 if (rdev->family >= CHIP_R420) { in radeon_read_clocks_OF()
129 p1pll->pll_in_min = 100; in radeon_read_clocks_OF()
130 p1pll->pll_in_max = 1350; in radeon_read_clocks_OF()
131 p1pll->pll_out_min = 20000; in radeon_read_clocks_OF()
132 p1pll->pll_out_max = 50000; in radeon_read_clocks_OF()
133 p2pll->pll_in_min = 100; in radeon_read_clocks_OF()
134 p2pll->pll_in_max = 1350; in radeon_read_clocks_OF()
135 p2pll->pll_out_min = 20000; in radeon_read_clocks_OF()
136 p2pll->pll_out_max = 50000; in radeon_read_clocks_OF()
138 p1pll->pll_in_min = 40; in radeon_read_clocks_OF()
139 p1pll->pll_in_max = 500; in radeon_read_clocks_OF()
140 p1pll->pll_out_min = 12500; in radeon_read_clocks_OF()
141 p1pll->pll_out_max = 35000; in radeon_read_clocks_OF()
142 p2pll->pll_in_min = 40; in radeon_read_clocks_OF()
143 p2pll->pll_in_max = 500; in radeon_read_clocks_OF()
144 p2pll->pll_out_min = 12500; in radeon_read_clocks_OF()
145 p2pll->pll_out_max = 35000; in radeon_read_clocks_OF()
148 rdev->clock.max_pixel_clock = 35000; in radeon_read_clocks_OF()
150 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
151 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
157 rdev->clock.default_sclk = (*val) / 10; in radeon_read_clocks_OF()
159 rdev->clock.default_sclk = in radeon_read_clocks_OF()
164 rdev->clock.default_mclk = (*val) / 10; in radeon_read_clocks_OF()
166 rdev->clock.default_mclk = in radeon_read_clocks_OF()
169 DRM_INFO("Using device-tree clock info\n"); in radeon_read_clocks_OF()
182 struct radeon_device *rdev = dev->dev_private; in radeon_get_clock_info()
183 struct radeon_pll *p1pll = &rdev->clock.p1pll; in radeon_get_clock_info()
184 struct radeon_pll *p2pll = &rdev->clock.p2pll; in radeon_get_clock_info()
185 struct radeon_pll *dcpll = &rdev->clock.dcpll; in radeon_get_clock_info()
186 struct radeon_pll *spll = &rdev->clock.spll; in radeon_get_clock_info()
187 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_get_clock_info()
190 if (rdev->is_atom_bios) in radeon_get_clock_info()
198 if (p1pll->reference_div < 2) { in radeon_get_clock_info()
202 p1pll->reference_div = in radeon_get_clock_info()
205 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; in radeon_get_clock_info()
206 if (p1pll->reference_div < 2) in radeon_get_clock_info()
207 p1pll->reference_div = 12; in radeon_get_clock_info()
209 p1pll->reference_div = 12; in radeon_get_clock_info()
211 if (p2pll->reference_div < 2) in radeon_get_clock_info()
212 p2pll->reference_div = 12; in radeon_get_clock_info()
213 if (rdev->family < CHIP_RS600) { in radeon_get_clock_info()
214 if (spll->reference_div < 2) in radeon_get_clock_info()
215 spll->reference_div = in radeon_get_clock_info()
219 if (mpll->reference_div < 2) in radeon_get_clock_info()
220 mpll->reference_div = spll->reference_div; in radeon_get_clock_info()
228 rdev->clock.max_pixel_clock = 35000; in radeon_get_clock_info()
230 if (rdev->flags & RADEON_IS_IGP) { in radeon_get_clock_info()
231 p1pll->reference_freq = 1432; in radeon_get_clock_info()
232 p2pll->reference_freq = 1432; in radeon_get_clock_info()
233 spll->reference_freq = 1432; in radeon_get_clock_info()
234 mpll->reference_freq = 1432; in radeon_get_clock_info()
236 p1pll->reference_freq = 2700; in radeon_get_clock_info()
237 p2pll->reference_freq = 2700; in radeon_get_clock_info()
238 spll->reference_freq = 2700; in radeon_get_clock_info()
239 mpll->reference_freq = 2700; in radeon_get_clock_info()
241 p1pll->reference_div = in radeon_get_clock_info()
243 if (p1pll->reference_div < 2) in radeon_get_clock_info()
244 p1pll->reference_div = 12; in radeon_get_clock_info()
245 p2pll->reference_div = p1pll->reference_div; in radeon_get_clock_info()
247 if (rdev->family >= CHIP_R420) { in radeon_get_clock_info()
248 p1pll->pll_in_min = 100; in radeon_get_clock_info()
249 p1pll->pll_in_max = 1350; in radeon_get_clock_info()
250 p1pll->pll_out_min = 20000; in radeon_get_clock_info()
251 p1pll->pll_out_max = 50000; in radeon_get_clock_info()
252 p2pll->pll_in_min = 100; in radeon_get_clock_info()
253 p2pll->pll_in_max = 1350; in radeon_get_clock_info()
254 p2pll->pll_out_min = 20000; in radeon_get_clock_info()
255 p2pll->pll_out_max = 50000; in radeon_get_clock_info()
257 p1pll->pll_in_min = 40; in radeon_get_clock_info()
258 p1pll->pll_in_max = 500; in radeon_get_clock_info()
259 p1pll->pll_out_min = 12500; in radeon_get_clock_info()
260 p1pll->pll_out_max = 35000; in radeon_get_clock_info()
261 p2pll->pll_in_min = 40; in radeon_get_clock_info()
262 p2pll->pll_in_max = 500; in radeon_get_clock_info()
263 p2pll->pll_out_min = 12500; in radeon_get_clock_info()
264 p2pll->pll_out_max = 35000; in radeon_get_clock_info()
267 spll->reference_div = in radeon_get_clock_info()
270 mpll->reference_div = spll->reference_div; in radeon_get_clock_info()
271 rdev->clock.default_sclk = in radeon_get_clock_info()
273 rdev->clock.default_mclk = in radeon_get_clock_info()
280 p1pll->min_post_div = 2; in radeon_get_clock_info()
281 p1pll->max_post_div = 0x7f; in radeon_get_clock_info()
282 p1pll->min_frac_feedback_div = 0; in radeon_get_clock_info()
283 p1pll->max_frac_feedback_div = 9; in radeon_get_clock_info()
284 p2pll->min_post_div = 2; in radeon_get_clock_info()
285 p2pll->max_post_div = 0x7f; in radeon_get_clock_info()
286 p2pll->min_frac_feedback_div = 0; in radeon_get_clock_info()
287 p2pll->max_frac_feedback_div = 9; in radeon_get_clock_info()
289 p1pll->min_post_div = 1; in radeon_get_clock_info()
290 p1pll->max_post_div = 16; in radeon_get_clock_info()
291 p1pll->min_frac_feedback_div = 0; in radeon_get_clock_info()
292 p1pll->max_frac_feedback_div = 0; in radeon_get_clock_info()
293 p2pll->min_post_div = 1; in radeon_get_clock_info()
294 p2pll->max_post_div = 12; in radeon_get_clock_info()
295 p2pll->min_frac_feedback_div = 0; in radeon_get_clock_info()
296 p2pll->max_frac_feedback_div = 0; in radeon_get_clock_info()
300 dcpll->min_post_div = 2; in radeon_get_clock_info()
301 dcpll->max_post_div = 0x7f; in radeon_get_clock_info()
302 dcpll->min_frac_feedback_div = 0; in radeon_get_clock_info()
303 dcpll->max_frac_feedback_div = 9; in radeon_get_clock_info()
304 dcpll->min_ref_div = 2; in radeon_get_clock_info()
305 dcpll->max_ref_div = 0x3ff; in radeon_get_clock_info()
306 dcpll->min_feedback_div = 4; in radeon_get_clock_info()
307 dcpll->max_feedback_div = 0xfff; in radeon_get_clock_info()
308 dcpll->best_vco = 0; in radeon_get_clock_info()
310 p1pll->min_ref_div = 2; in radeon_get_clock_info()
311 p1pll->max_ref_div = 0x3ff; in radeon_get_clock_info()
312 p1pll->min_feedback_div = 4; in radeon_get_clock_info()
313 p1pll->max_feedback_div = 0x7ff; in radeon_get_clock_info()
314 p1pll->best_vco = 0; in radeon_get_clock_info()
316 p2pll->min_ref_div = 2; in radeon_get_clock_info()
317 p2pll->max_ref_div = 0x3ff; in radeon_get_clock_info()
318 p2pll->min_feedback_div = 4; in radeon_get_clock_info()
319 p2pll->max_feedback_div = 0x7ff; in radeon_get_clock_info()
320 p2pll->best_vco = 0; in radeon_get_clock_info()
323 spll->min_post_div = 1; in radeon_get_clock_info()
324 spll->max_post_div = 1; in radeon_get_clock_info()
325 spll->min_ref_div = 2; in radeon_get_clock_info()
326 spll->max_ref_div = 0xff; in radeon_get_clock_info()
327 spll->min_feedback_div = 4; in radeon_get_clock_info()
328 spll->max_feedback_div = 0xff; in radeon_get_clock_info()
329 spll->best_vco = 0; in radeon_get_clock_info()
332 mpll->min_post_div = 1; in radeon_get_clock_info()
333 mpll->max_post_div = 1; in radeon_get_clock_info()
334 mpll->min_ref_div = 2; in radeon_get_clock_info()
335 mpll->max_ref_div = 0xff; in radeon_get_clock_info()
336 mpll->min_feedback_div = 4; in radeon_get_clock_info()
337 mpll->max_feedback_div = 0xff; in radeon_get_clock_info()
338 mpll->best_vco = 0; in radeon_get_clock_info()
340 if (!rdev->clock.default_sclk) in radeon_get_clock_info()
341 rdev->clock.default_sclk = radeon_get_engine_clock(rdev); in radeon_get_clock_info()
342 if ((!rdev->clock.default_mclk) && rdev->asic->pm.get_memory_clock) in radeon_get_clock_info()
343 rdev->clock.default_mclk = radeon_get_memory_clock(rdev); in radeon_get_clock_info()
345 rdev->pm.current_sclk = rdev->clock.default_sclk; in radeon_get_clock_info()
346 rdev->pm.current_mclk = rdev->clock.default_mclk; in radeon_get_clock_info()
355 struct radeon_pll *spll = &rdev->clock.spll; in calc_eng_mem_clock()
356 int ref_div = spll->reference_div; in calc_eng_mem_clock()
376 req_clock += spll->reference_freq; in calc_eng_mem_clock()
377 req_clock /= (2 * spll->reference_freq); in calc_eng_mem_clock()
382 req_clock *= spll->reference_freq; in calc_eng_mem_clock()
481 if (rdev->flags & RADEON_SINGLE_CRTC) { in radeon_legacy_set_clock_gating()
498 if ((rdev->family == CHIP_RS400) || in radeon_legacy_set_clock_gating()
499 (rdev->family == CHIP_RS480)) { in radeon_legacy_set_clock_gating()
546 } else if (rdev->family >= CHIP_RV350) { in radeon_legacy_set_clock_gating()
621 if (rdev->mc.vram_width == 64) { in radeon_legacy_set_clock_gating()
674 if (((rdev->family == CHIP_RV250) && in radeon_legacy_set_clock_gating()
678 || ((rdev->family == CHIP_RV100) in radeon_legacy_set_clock_gating()
689 if ((rdev->family == CHIP_RV200) || in radeon_legacy_set_clock_gating()
690 (rdev->family == CHIP_RV250) || in radeon_legacy_set_clock_gating()
691 (rdev->family == CHIP_RV280)) { in radeon_legacy_set_clock_gating()
696 if (((rdev->family == CHIP_RV200) || in radeon_legacy_set_clock_gating()
697 (rdev->family == CHIP_RV250)) && in radeon_legacy_set_clock_gating()
708 if (((rdev->family == CHIP_RV200) || in radeon_legacy_set_clock_gating()
709 (rdev->family == CHIP_RV250)) && in radeon_legacy_set_clock_gating()
741 if (rdev->flags & RADEON_SINGLE_CRTC) { in radeon_legacy_set_clock_gating()
751 } else if ((rdev->family == CHIP_RS400) || in radeon_legacy_set_clock_gating()
752 (rdev->family == CHIP_RS480)) { in radeon_legacy_set_clock_gating()
790 } else if (rdev->family >= CHIP_RV350) { in radeon_legacy_set_clock_gating()
846 if (rdev->flags & RADEON_SINGLE_CRTC) { in radeon_legacy_set_clock_gating()
858 } else if ((rdev->family == CHIP_R300) || in radeon_legacy_set_clock_gating()
859 (rdev->family == CHIP_R350)) { in radeon_legacy_set_clock_gating()
871 if ((rdev->family == CHIP_R300) || in radeon_legacy_set_clock_gating()
872 (rdev->family == CHIP_R350)) { in radeon_legacy_set_clock_gating()
881 if (rdev->flags & RADEON_IS_IGP) { in radeon_legacy_set_clock_gating()
889 if ((rdev->family == CHIP_RV200) || in radeon_legacy_set_clock_gating()
890 (rdev->family == CHIP_RV250) || in radeon_legacy_set_clock_gating()
891 (rdev->family == CHIP_RV280)) { in radeon_legacy_set_clock_gating()