2379 	struct radeon_bo_list *src_reloc, *dst_reloc;  in r600_dma_cs_parse()  local
2400 			r = r600_dma_cs_next_reloc(p, &dst_reloc);  in r600_dma_cs_parse()
2409 				ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);  in r600_dma_cs_parse()
2415 				ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2416 				ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2419 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2421 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2431 			r = r600_dma_cs_next_reloc(p, &dst_reloc);  in r600_dma_cs_parse()
2447 					ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2448 					ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2458 					ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);  in r600_dma_cs_parse()
2468 					ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2470 					ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2479 					ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2482 					ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16;  in r600_dma_cs_parse()
2491 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2493 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2502 			r = r600_dma_cs_next_reloc(p, &dst_reloc);  in r600_dma_cs_parse()
2509 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2511 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2514 			ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2515 			ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;  in r600_dma_cs_parse()