Lines Matching refs:p
349 static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) in r600_cs_track_validate_cb() argument
351 struct r600_cs_track *track = p->track; in r600_cs_track_validate_cb()
356 volatile u32 *ib = p->ib.ptr; in r600_cs_track_validate_cb()
364 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", in r600_cs_track_validate_cb()
387 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, in r600_cs_track_validate_cb()
405 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, in r600_cs_track_validate_cb()
412 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n", in r600_cs_track_validate_cb()
417 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n", in r600_cs_track_validate_cb()
422 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i, in r600_cs_track_validate_cb()
450 dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n", in r600_cs_track_validate_cb()
481 dev_warn(p->dev, "%s FMASK_TILE_MAX too large " in r600_cs_track_validate_cb()
499 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large " in r600_cs_track_validate_cb()
509 dev_warn(p->dev, "%s invalid tile mode\n", __func__); in r600_cs_track_validate_cb()
515 static int r600_cs_track_validate_db(struct radeon_cs_parser *p) in r600_cs_track_validate_db() argument
517 struct r600_cs_track *track = p->track; in r600_cs_track_validate_db()
525 volatile u32 *ib = p->ib.ptr; in r600_cs_track_validate_db()
529 dev_warn(p->dev, "z/stencil with no depth buffer\n"); in r600_cs_track_validate_db()
547 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info)); in r600_cs_track_validate_db()
552 dev_warn(p->dev, "z/stencil buffer size not set\n"); in r600_cs_track_validate_db()
558 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n", in r600_cs_track_validate_db()
582 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, in r600_cs_track_validate_db()
595 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, in r600_cs_track_validate_db()
602 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n", in r600_cs_track_validate_db()
607 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n", in r600_cs_track_validate_db()
612 dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__, in r600_cs_track_validate_db()
621 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n", in r600_cs_track_validate_db()
635 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n", in r600_cs_track_validate_db()
640 dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n", in r600_cs_track_validate_db()
679 dev_warn(p->dev, "%s:%d invalid num pipes %d\n", in r600_cs_track_validate_db()
692 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n", in r600_cs_track_validate_db()
703 static int r600_cs_track_check(struct radeon_cs_parser *p) in r600_cs_track_check() argument
705 struct r600_cs_track *track = p->track; in r600_cs_track_check()
710 if (p->rdev == NULL) in r600_cs_track_check()
727 dev_warn(p->dev, "No buffer for streamout %d\n", i); in r600_cs_track_check()
756 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", in r600_cs_track_check()
761 r = r600_cs_track_validate_cb(p, i); in r600_cs_track_check()
774 r = r600_cs_track_validate_db(p); in r600_cs_track_check()
791 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p) in r600_cs_packet_parse_vline() argument
798 return r600_cs_common_vline_parse(p, vline_start_end, vline_status); in r600_cs_packet_parse_vline()
822 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, in r600_cs_common_vline_parse() argument
834 ib = p->ib.ptr; in r600_cs_common_vline_parse()
837 r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx); in r600_cs_common_vline_parse()
848 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); in r600_cs_common_vline_parse()
864 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) { in r600_cs_common_vline_parse()
869 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) { in r600_cs_common_vline_parse()
875 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2); in r600_cs_common_vline_parse()
879 h_idx = p->idx - 2; in r600_cs_common_vline_parse()
880 p->idx += wait_reg_mem.count + 2; in r600_cs_common_vline_parse()
881 p->idx += p3reloc.count + 2; in r600_cs_common_vline_parse()
883 header = radeon_get_ib_value(p, h_idx); in r600_cs_common_vline_parse()
884 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); in r600_cs_common_vline_parse()
887 crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id); in r600_cs_common_vline_parse()
916 static int r600_packet0_check(struct radeon_cs_parser *p, in r600_packet0_check() argument
924 r = r600_cs_packet_parse_vline(p); in r600_packet0_check()
938 static int r600_cs_parse_packet0(struct radeon_cs_parser *p, in r600_cs_parse_packet0() argument
948 r = r600_packet0_check(p, pkt, idx, reg); in r600_cs_parse_packet0()
966 static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) in r600_cs_check_reg() argument
968 struct r600_cs_track *track = (struct r600_cs_track *)p->track; in r600_cs_check_reg()
975 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in r600_cs_check_reg()
981 ib = p->ib.ptr; in r600_cs_check_reg()
1014 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in r600_cs_check_reg()
1016 dev_warn(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1023 track->sq_config = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1026 track->db_depth_control = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1030 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && in r600_cs_check_reg()
1031 radeon_cs_packet_next_is_pkt3_nop(p)) { in r600_cs_check_reg()
1032 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1034 dev_warn(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1038 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1049 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1054 track->db_depth_view = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1058 track->db_depth_size = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1063 track->vgt_strmout_en = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1067 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1074 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1076 dev_warn(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1081 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1093 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in r600_cs_check_reg()
1097 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1099 dev_warn(p->dev, "missing reloc for CP_COHER_BASE " in r600_cs_check_reg()
1106 track->cb_target_mask = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1110 track->cb_shader_mask = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1113 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx)); in r600_cs_check_reg()
1119 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx)); in r600_cs_check_reg()
1131 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && in r600_cs_check_reg()
1132 radeon_cs_packet_next_is_pkt3_nop(p)) { in r600_cs_check_reg()
1133 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1135 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); in r600_cs_check_reg()
1139 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1149 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1162 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1174 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1196 if (!radeon_cs_packet_next_is_pkt3_nop(p)) { in r600_cs_check_reg()
1198 …dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n… in r600_cs_check_reg()
1205 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1207 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); in r600_cs_check_reg()
1227 if (!radeon_cs_packet_next_is_pkt3_nop(p)) { in r600_cs_check_reg()
1229 …dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n… in r600_cs_check_reg()
1236 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1238 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); in r600_cs_check_reg()
1258 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1271 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1273 dev_warn(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1278 track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1286 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1288 dev_warn(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1292 track->db_offset = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1299 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1301 dev_warn(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1305 track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1311 track->htile_surface = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1369 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1371 dev_warn(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1378 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_cs_check_reg()
1380 dev_warn(p->dev, "bad SET_CONFIG_REG " in r600_cs_check_reg()
1387 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in r600_cs_check_reg()
1390 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in r600_cs_check_reg()
1469 static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, in r600_check_texture_resource() argument
1476 struct r600_cs_track *track = p->track; in r600_check_texture_resource()
1487 if (p->rdev == NULL) in r600_check_texture_resource()
1494 word0 = radeon_get_ib_value(p, idx + 0); in r600_check_texture_resource()
1495 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in r600_check_texture_resource()
1501 word1 = radeon_get_ib_value(p, idx + 1); in r600_check_texture_resource()
1502 word2 = radeon_get_ib_value(p, idx + 2) << 8; in r600_check_texture_resource()
1503 word3 = radeon_get_ib_value(p, idx + 3) << 8; in r600_check_texture_resource()
1504 word4 = radeon_get_ib_value(p, idx + 4); in r600_check_texture_resource()
1505 word5 = radeon_get_ib_value(p, idx + 5); in r600_check_texture_resource()
1529 if (p->family >= CHIP_RV770) in r600_check_texture_resource()
1546 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0)); in r600_check_texture_resource()
1549 if (!r600_fmt_is_valid_texture(format, p->family)) { in r600_check_texture_resource()
1550 dev_warn(p->dev, "%s:%d texture invalid format %d\n", in r600_check_texture_resource()
1557 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n", in r600_check_texture_resource()
1565 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n", in r600_check_texture_resource()
1570 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n", in r600_check_texture_resource()
1575 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n", in r600_check_texture_resource()
1581 dev_warn(p->dev, "texture blevel %d > llevel %d\n", in r600_check_texture_resource()
1595 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n", in r600_check_texture_resource()
1599 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align); in r600_check_texture_resource()
1610 static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) in r600_is_safe_reg() argument
1616 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in r600_is_safe_reg()
1622 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in r600_is_safe_reg()
1626 static int r600_packet3_check(struct radeon_cs_parser *p, in r600_packet3_check() argument
1638 track = (struct r600_cs_track *)p->track; in r600_packet3_check()
1639 ib = p->ib.ptr; in r600_packet3_check()
1641 idx_value = radeon_get_ib_value(p, idx); in r600_packet3_check()
1655 tmp = radeon_get_ib_value(p, idx + 1); in r600_packet3_check()
1667 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1683 if (p->family >= CHIP_RV770 || pkt->count) { in r600_packet3_check()
1708 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1716 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in r600_packet3_check()
1721 r = r600_cs_track_check(p); in r600_packet3_check()
1723 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in r600_packet3_check()
1733 r = r600_cs_track_check(p); in r600_packet3_check()
1735 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in r600_packet3_check()
1745 r = r600_cs_track_check(p); in r600_packet3_check()
1747 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in r600_packet3_check()
1760 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1767 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + in r600_packet3_check()
1768 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in r600_packet3_check()
1785 command = radeon_get_ib_value(p, idx+4); in r600_packet3_check()
1797 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1803 tmp = radeon_get_ib_value(p, idx) + in r600_packet3_check()
1804 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in r600_packet3_check()
1809 dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n", in r600_packet3_check()
1827 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1833 tmp = radeon_get_ib_value(p, idx+2) + in r600_packet3_check()
1834 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); in r600_packet3_check()
1839 dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", in r600_packet3_check()
1855 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || in r600_packet3_check()
1856 radeon_get_ib_value(p, idx + 2) != 0) { in r600_packet3_check()
1857 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1873 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1879 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + in r600_packet3_check()
1880 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in r600_packet3_check()
1894 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1901 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in r600_packet3_check()
1902 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in r600_packet3_check()
1919 r = r600_cs_check_reg(p, reg, idx+1+i); in r600_packet3_check()
1935 r = r600_cs_check_reg(p, reg, idx+1+i); in r600_packet3_check()
1957 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { in r600_packet3_check()
1960 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1966 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in r600_packet3_check()
1974 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
1981 r = r600_check_texture_resource(p, idx+(i*7)+1, in r600_packet3_check()
1983 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2), in r600_packet3_check()
1984 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3), in r600_packet3_check()
1995 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
2000 offset = radeon_get_ib_value(p, idx+1+(i*7)+0); in r600_packet3_check()
2001 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1; in r600_packet3_check()
2002 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { in r600_packet3_check()
2004 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n", in r600_packet3_check()
2081 if (p->family < CHIP_RS780) { in r600_packet3_check()
2096 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
2107 offset = radeon_get_ib_value(p, idx+1) << 8; in r600_packet3_check()
2123 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) { in r600_packet3_check()
2140 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
2145 offset = radeon_get_ib_value(p, idx+1); in r600_packet3_check()
2146 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in r600_packet3_check()
2159 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
2164 offset = radeon_get_ib_value(p, idx+3); in r600_packet3_check()
2165 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in r600_packet3_check()
2184 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
2189 offset = radeon_get_ib_value(p, idx+0); in r600_packet3_check()
2190 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; in r600_packet3_check()
2213 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
2218 offset = radeon_get_ib_value(p, idx+1); in r600_packet3_check()
2219 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in r600_packet3_check()
2230 reg = radeon_get_ib_value(p, idx+1) << 2; in r600_packet3_check()
2231 if (!r600_is_safe_reg(p, reg, idx+1)) in r600_packet3_check()
2237 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); in r600_packet3_check()
2242 offset = radeon_get_ib_value(p, idx+3); in r600_packet3_check()
2243 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in r600_packet3_check()
2254 reg = radeon_get_ib_value(p, idx+3) << 2; in r600_packet3_check()
2255 if (!r600_is_safe_reg(p, reg, idx+3)) in r600_packet3_check()
2268 int r600_cs_parse(struct radeon_cs_parser *p) in r600_cs_parse() argument
2274 if (p->track == NULL) { in r600_cs_parse()
2280 if (p->rdev->family < CHIP_RV770) { in r600_cs_parse()
2281 track->npipes = p->rdev->config.r600.tiling_npipes; in r600_cs_parse()
2282 track->nbanks = p->rdev->config.r600.tiling_nbanks; in r600_cs_parse()
2283 track->group_size = p->rdev->config.r600.tiling_group_size; in r600_cs_parse()
2284 } else if (p->rdev->family <= CHIP_RV740) { in r600_cs_parse()
2285 track->npipes = p->rdev->config.rv770.tiling_npipes; in r600_cs_parse()
2286 track->nbanks = p->rdev->config.rv770.tiling_nbanks; in r600_cs_parse()
2287 track->group_size = p->rdev->config.rv770.tiling_group_size; in r600_cs_parse()
2289 p->track = track; in r600_cs_parse()
2292 r = radeon_cs_packet_parse(p, &pkt, p->idx); in r600_cs_parse()
2294 kfree(p->track); in r600_cs_parse()
2295 p->track = NULL; in r600_cs_parse()
2298 p->idx += pkt.count + 2; in r600_cs_parse()
2301 r = r600_cs_parse_packet0(p, &pkt); in r600_cs_parse()
2306 r = r600_packet3_check(p, &pkt); in r600_cs_parse()
2310 kfree(p->track); in r600_cs_parse()
2311 p->track = NULL; in r600_cs_parse()
2315 kfree(p->track); in r600_cs_parse()
2316 p->track = NULL; in r600_cs_parse()
2319 } while (p->idx < p->chunk_ib->length_dw); in r600_cs_parse()
2321 for (r = 0; r < p->ib.length_dw; r++) { in r600_cs_parse()
2322 pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]); in r600_cs_parse()
2326 kfree(p->track); in r600_cs_parse()
2327 p->track = NULL; in r600_cs_parse()
2342 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p, in r600_dma_cs_next_reloc() argument
2348 if (p->chunk_relocs == NULL) { in r600_dma_cs_next_reloc()
2352 idx = p->dma_reloc_idx; in r600_dma_cs_next_reloc()
2353 if (idx >= p->nrelocs) { in r600_dma_cs_next_reloc()
2355 idx, p->nrelocs); in r600_dma_cs_next_reloc()
2358 *cs_reloc = &p->relocs[idx]; in r600_dma_cs_next_reloc()
2359 p->dma_reloc_idx++; in r600_dma_cs_next_reloc()
2376 int r600_dma_cs_parse(struct radeon_cs_parser *p) in r600_dma_cs_parse() argument
2378 struct radeon_cs_chunk *ib_chunk = p->chunk_ib; in r600_dma_cs_parse()
2381 volatile u32 *ib = p->ib.ptr; in r600_dma_cs_parse()
2387 if (p->idx >= ib_chunk->length_dw) { in r600_dma_cs_parse()
2389 p->idx, ib_chunk->length_dw); in r600_dma_cs_parse()
2392 idx = p->idx; in r600_dma_cs_parse()
2393 header = radeon_get_ib_value(p, idx); in r600_dma_cs_parse()
2400 r = r600_dma_cs_next_reloc(p, &dst_reloc); in r600_dma_cs_parse()
2406 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2410 p->idx += count + 5; in r600_dma_cs_parse()
2412 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2413 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in r600_dma_cs_parse()
2417 p->idx += count + 3; in r600_dma_cs_parse()
2420 dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n", in r600_dma_cs_parse()
2426 r = r600_dma_cs_next_reloc(p, &src_reloc); in r600_dma_cs_parse()
2431 r = r600_dma_cs_next_reloc(p, &dst_reloc); in r600_dma_cs_parse()
2437 idx_value = radeon_get_ib_value(p, idx + 2); in r600_dma_cs_parse()
2441 src_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2445 dst_offset = radeon_get_ib_value(p, idx+5); in r600_dma_cs_parse()
2446 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in r600_dma_cs_parse()
2451 src_offset = radeon_get_ib_value(p, idx+5); in r600_dma_cs_parse()
2452 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in r600_dma_cs_parse()
2456 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2460 p->idx += 7; in r600_dma_cs_parse()
2462 if (p->family >= CHIP_RV770) { in r600_dma_cs_parse()
2463 src_offset = radeon_get_ib_value(p, idx+2); in r600_dma_cs_parse()
2464 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in r600_dma_cs_parse()
2465 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2466 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in r600_dma_cs_parse()
2472 p->idx += 5; in r600_dma_cs_parse()
2474 src_offset = radeon_get_ib_value(p, idx+2); in r600_dma_cs_parse()
2475 src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in r600_dma_cs_parse()
2476 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2477 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16; in r600_dma_cs_parse()
2483 p->idx += 4; in r600_dma_cs_parse()
2487 dev_warn(p->dev, "DMA copy src buffer too small (%llu %lu)\n", in r600_dma_cs_parse()
2492 dev_warn(p->dev, "DMA write dst buffer too small (%llu %lu)\n", in r600_dma_cs_parse()
2498 if (p->family < CHIP_RV770) { in r600_dma_cs_parse()
2502 r = r600_dma_cs_next_reloc(p, &dst_reloc); in r600_dma_cs_parse()
2507 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2508 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; in r600_dma_cs_parse()
2510 dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n", in r600_dma_cs_parse()
2516 p->idx += 4; in r600_dma_cs_parse()
2519 p->idx += 1; in r600_dma_cs_parse()
2525 } while (p->idx < p->chunk_ib->length_dw); in r600_dma_cs_parse()
2527 for (r = 0; r < p->ib->length_dw; r++) { in r600_dma_cs_parse()
2528 pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]); in r600_dma_cs_parse()