Lines Matching refs:speed_cntl
4487 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; in r600_pcie_gen2_enable() local
4511 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in r600_pcie_gen2_enable()
4512 if (speed_cntl & LC_CURRENT_DATA_RATE) { in r600_pcie_gen2_enable()
4540 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in r600_pcie_gen2_enable()
4541 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && in r600_pcie_gen2_enable()
4542 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { in r600_pcie_gen2_enable()
4556 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; in r600_pcie_gen2_enable()
4557 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); in r600_pcie_gen2_enable()
4558 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; in r600_pcie_gen2_enable()
4559 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; in r600_pcie_gen2_enable()
4560 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; in r600_pcie_gen2_enable()
4561 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in r600_pcie_gen2_enable()
4579 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in r600_pcie_gen2_enable()
4580 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; in r600_pcie_gen2_enable()
4581 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in r600_pcie_gen2_enable()
4584 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in r600_pcie_gen2_enable()
4585 speed_cntl |= LC_GEN2_EN_STRAP; in r600_pcie_gen2_enable()
4586 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in r600_pcie_gen2_enable()