3512 					   struct radeon_ps *new_ps,  in ni_set_uvd_clock_before_set_eng_clock()  argument
3515 	struct ni_ps *new_state = ni_get_ps(new_ps);  in ni_set_uvd_clock_before_set_eng_clock()
3518 	if ((new_ps->vclk == old_ps->vclk) &&  in ni_set_uvd_clock_before_set_eng_clock()
3519 	    (new_ps->dclk == old_ps->dclk))  in ni_set_uvd_clock_before_set_eng_clock()
3526 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);  in ni_set_uvd_clock_before_set_eng_clock()
3530 					  struct radeon_ps *new_ps,  in ni_set_uvd_clock_after_set_eng_clock()  argument
3533 	struct ni_ps *new_state = ni_get_ps(new_ps);  in ni_set_uvd_clock_after_set_eng_clock()
3536 	if ((new_ps->vclk == old_ps->vclk) &&  in ni_set_uvd_clock_after_set_eng_clock()
3537 	    (new_ps->dclk == old_ps->dclk))  in ni_set_uvd_clock_after_set_eng_clock()
3544 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);  in ni_set_uvd_clock_after_set_eng_clock()
3567 	struct ni_ps *new_ps = ni_get_ps(rps);  in ni_update_current_ps()  local
3572 	ni_pi->current_ps = *new_ps;  in ni_update_current_ps()
3579 	struct ni_ps *new_ps = ni_get_ps(rps);  in ni_update_requested_ps()  local
3584 	ni_pi->requested_ps = *new_ps;  in ni_update_requested_ps()
3746 	struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;  in ni_power_control_set_level()  local
3755 	ret = ni_populate_smc_tdp_limits(rdev, new_ps);  in ni_power_control_set_level()
3772 	struct radeon_ps *new_ps = &requested_ps;  in ni_dpm_pre_set_power_state()  local
3774 	ni_update_requested_ps(rdev, new_ps);  in ni_dpm_pre_set_power_state()
3784 	struct radeon_ps *new_ps = &eg_pi->requested_rps;  in ni_dpm_set_power_state()  local
3793 	ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);  in ni_dpm_set_power_state()
3794 	ret = ni_enable_power_containment(rdev, new_ps, false);  in ni_dpm_set_power_state()
3799 	ret = ni_enable_smc_cac(rdev, new_ps, false);  in ni_dpm_set_power_state()
3810 		btc_notify_uvd_to_smc(rdev, new_ps);  in ni_dpm_set_power_state()
3811 	ret = ni_upload_sw_state(rdev, new_ps);  in ni_dpm_set_power_state()
3817 		ret = ni_upload_mc_reg_table(rdev, new_ps);  in ni_dpm_set_power_state()
3823 	ret = ni_program_memory_timing_parameters(rdev, new_ps);  in ni_dpm_set_power_state()
3838 	ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);  in ni_dpm_set_power_state()
3839 	ret = ni_enable_smc_cac(rdev, new_ps, true);  in ni_dpm_set_power_state()
3844 	ret = ni_enable_power_containment(rdev, new_ps, true);  in ni_dpm_set_power_state()
3863 	struct radeon_ps *new_ps = &eg_pi->requested_rps;  in ni_dpm_post_set_power_state()  local
3865 	ni_update_current_ps(rdev, new_ps);  in ni_dpm_post_set_power_state()