Lines Matching refs:u32
45 u32 offset;
46 u32 mask;
47 u32 shift;
48 u32 value;
53 u32 block_id;
54 u32 signal_id;
55 u32 t;
59 u32 cntl;
60 u32 block_mask;
61 u32 block_shift;
62 u32 signal_mask;
63 u32 signal_shift;
64 u32 t_mask;
65 u32 t_shift;
66 u32 enable_mask;
67 u32 enable_shift;
71 u32 sclk;
83 u32 num_levels;
92 u32 bootup_uma_clk;
93 u32 bootup_sclk;
94 u32 dentist_vco_freq;
95 u32 nb_dpm_enable;
96 u32 nbp_memory_clock[KV_NUM_NBPSTATES];
97 u32 nbp_n_clock[KV_NUM_NBPSTATES];
103 u32 uma_channel_number;
107 u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];
108 u32 voltage_drop_t;
115 u32 lowest_valid;
116 u32 highest_valid;
121 u32 sram_end;
122 u32 dpm_table_start;
123 u32 soft_regs_start;
152 u32 low_sclk_interrupt_t;
188 int kv_notify_message_to_smu(struct radeon_device *rdev, u32 id);
189 int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask);
191 PPSMC_Msg msg, u32 parameter);
192 int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
193 u32 *value, u32 limit);
197 u32 smc_start_address,
198 const u8 *src, u32 byte_count, u32 limit);