Lines Matching refs:track
117 static void evergreen_cs_track_init(struct evergreen_cs_track *track) in evergreen_cs_track_init() argument
122 track->cb_color_fmask_bo[i] = NULL; in evergreen_cs_track_init()
123 track->cb_color_cmask_bo[i] = NULL; in evergreen_cs_track_init()
124 track->cb_color_cmask_slice[i] = 0; in evergreen_cs_track_init()
125 track->cb_color_fmask_slice[i] = 0; in evergreen_cs_track_init()
129 track->cb_color_bo[i] = NULL; in evergreen_cs_track_init()
130 track->cb_color_bo_offset[i] = 0xFFFFFFFF; in evergreen_cs_track_init()
131 track->cb_color_info[i] = 0; in evergreen_cs_track_init()
132 track->cb_color_view[i] = 0xFFFFFFFF; in evergreen_cs_track_init()
133 track->cb_color_pitch[i] = 0; in evergreen_cs_track_init()
134 track->cb_color_slice[i] = 0xfffffff; in evergreen_cs_track_init()
135 track->cb_color_slice_idx[i] = 0; in evergreen_cs_track_init()
137 track->cb_target_mask = 0xFFFFFFFF; in evergreen_cs_track_init()
138 track->cb_shader_mask = 0xFFFFFFFF; in evergreen_cs_track_init()
139 track->cb_dirty = true; in evergreen_cs_track_init()
141 track->db_depth_slice = 0xffffffff; in evergreen_cs_track_init()
142 track->db_depth_view = 0xFFFFC000; in evergreen_cs_track_init()
143 track->db_depth_size = 0xFFFFFFFF; in evergreen_cs_track_init()
144 track->db_depth_control = 0xFFFFFFFF; in evergreen_cs_track_init()
145 track->db_z_info = 0xFFFFFFFF; in evergreen_cs_track_init()
146 track->db_z_read_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
147 track->db_z_write_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
148 track->db_z_read_bo = NULL; in evergreen_cs_track_init()
149 track->db_z_write_bo = NULL; in evergreen_cs_track_init()
150 track->db_s_info = 0xFFFFFFFF; in evergreen_cs_track_init()
151 track->db_s_read_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
152 track->db_s_write_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
153 track->db_s_read_bo = NULL; in evergreen_cs_track_init()
154 track->db_s_write_bo = NULL; in evergreen_cs_track_init()
155 track->db_dirty = true; in evergreen_cs_track_init()
156 track->htile_bo = NULL; in evergreen_cs_track_init()
157 track->htile_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
158 track->htile_surface = 0; in evergreen_cs_track_init()
161 track->vgt_strmout_size[i] = 0; in evergreen_cs_track_init()
162 track->vgt_strmout_bo[i] = NULL; in evergreen_cs_track_init()
163 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; in evergreen_cs_track_init()
165 track->streamout_dirty = true; in evergreen_cs_track_init()
166 track->sx_misc_kill_all_prims = false; in evergreen_cs_track_init()
204 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_linear_aligned() local
207 palign = MAX(64, track->group_size / surf->bpe); in evergreen_surface_check_linear_aligned()
209 surf->base_align = track->group_size; in evergreen_surface_check_linear_aligned()
226 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_1d() local
229 palign = track->group_size / (8 * surf->bpe * surf->nsamples); in evergreen_surface_check_1d()
232 surf->base_align = track->group_size; in evergreen_surface_check_1d()
239 track->group_size, surf->bpe, surf->nsamples); in evergreen_surface_check_1d()
257 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_2d() local
268 palign = (8 * surf->bankw * track->npipes) * surf->mtilea; in evergreen_surface_check_2d()
395 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_cb() local
401 mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1; in evergreen_cs_track_validate_cb()
402 pitch = track->cb_color_pitch[id]; in evergreen_cs_track_validate_cb()
403 slice = track->cb_color_slice[id]; in evergreen_cs_track_validate_cb()
406 surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]); in evergreen_cs_track_validate_cb()
407 surf.format = G_028C70_FORMAT(track->cb_color_info[id]); in evergreen_cs_track_validate_cb()
408 surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
409 surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
410 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
411 surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
412 surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
418 id, track->cb_color_info[id]); in evergreen_cs_track_validate_cb()
430 __func__, __LINE__, id, track->cb_color_pitch[id], in evergreen_cs_track_validate_cb()
431 track->cb_color_slice[id], track->cb_color_attrib[id], in evergreen_cs_track_validate_cb()
432 track->cb_color_info[id]); in evergreen_cs_track_validate_cb()
436 offset = track->cb_color_bo_offset[id] << 8; in evergreen_cs_track_validate_cb()
444 if (offset > radeon_bo_size(track->cb_color_bo[id])) { in evergreen_cs_track_validate_cb()
457 bsize = radeon_bo_size(track->cb_color_bo[id]); in evergreen_cs_track_validate_cb()
458 tmp = track->cb_color_bo_offset[id] << 8; in evergreen_cs_track_validate_cb()
472 ib[track->cb_color_slice_idx[id]] = slice; in evergreen_cs_track_validate_cb()
481 track->cb_color_bo_offset[id] << 8, mslice, in evergreen_cs_track_validate_cb()
482 radeon_bo_size(track->cb_color_bo[id]), slice); in evergreen_cs_track_validate_cb()
498 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_htile() local
501 if (track->htile_bo == NULL) { in evergreen_cs_track_validate_htile()
503 __func__, __LINE__, track->db_z_info); in evergreen_cs_track_validate_htile()
507 if (G_028ABC_LINEAR(track->htile_surface)) { in evergreen_cs_track_validate_htile()
511 nby = round_up(nby, track->npipes * 8); in evergreen_cs_track_validate_htile()
517 switch (track->npipes) { in evergreen_cs_track_validate_htile()
540 __func__, __LINE__, track->npipes); in evergreen_cs_track_validate_htile()
548 size = roundup(nbx * nby * 4, track->npipes * (2 << 10)); in evergreen_cs_track_validate_htile()
549 size += track->htile_offset; in evergreen_cs_track_validate_htile()
551 if (size > radeon_bo_size(track->htile_bo)) { in evergreen_cs_track_validate_htile()
553 __func__, __LINE__, radeon_bo_size(track->htile_bo), in evergreen_cs_track_validate_htile()
562 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_stencil() local
568 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; in evergreen_cs_track_validate_stencil()
569 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); in evergreen_cs_track_validate_stencil()
570 slice = track->db_depth_slice; in evergreen_cs_track_validate_stencil()
573 surf.mode = G_028040_ARRAY_MODE(track->db_z_info); in evergreen_cs_track_validate_stencil()
574 surf.format = G_028044_FORMAT(track->db_s_info); in evergreen_cs_track_validate_stencil()
575 surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info); in evergreen_cs_track_validate_stencil()
576 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); in evergreen_cs_track_validate_stencil()
577 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); in evergreen_cs_track_validate_stencil()
578 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); in evergreen_cs_track_validate_stencil()
579 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); in evergreen_cs_track_validate_stencil()
605 __func__, __LINE__, track->db_depth_size, in evergreen_cs_track_validate_stencil()
606 track->db_depth_slice, track->db_s_info, track->db_z_info); in evergreen_cs_track_validate_stencil()
611 offset = track->db_s_read_offset << 8; in evergreen_cs_track_validate_stencil()
618 if (offset > radeon_bo_size(track->db_s_read_bo)) { in evergreen_cs_track_validate_stencil()
622 (unsigned long)track->db_s_read_offset << 8, mslice, in evergreen_cs_track_validate_stencil()
623 radeon_bo_size(track->db_s_read_bo)); in evergreen_cs_track_validate_stencil()
625 __func__, __LINE__, track->db_depth_size, in evergreen_cs_track_validate_stencil()
626 track->db_depth_slice, track->db_s_info, track->db_z_info); in evergreen_cs_track_validate_stencil()
630 offset = track->db_s_write_offset << 8; in evergreen_cs_track_validate_stencil()
637 if (offset > radeon_bo_size(track->db_s_write_bo)) { in evergreen_cs_track_validate_stencil()
641 (unsigned long)track->db_s_write_offset << 8, mslice, in evergreen_cs_track_validate_stencil()
642 radeon_bo_size(track->db_s_write_bo)); in evergreen_cs_track_validate_stencil()
647 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) { in evergreen_cs_track_validate_stencil()
659 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_depth() local
665 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; in evergreen_cs_track_validate_depth()
666 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); in evergreen_cs_track_validate_depth()
667 slice = track->db_depth_slice; in evergreen_cs_track_validate_depth()
670 surf.mode = G_028040_ARRAY_MODE(track->db_z_info); in evergreen_cs_track_validate_depth()
671 surf.format = G_028040_FORMAT(track->db_z_info); in evergreen_cs_track_validate_depth()
672 surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info); in evergreen_cs_track_validate_depth()
673 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); in evergreen_cs_track_validate_depth()
674 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); in evergreen_cs_track_validate_depth()
675 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); in evergreen_cs_track_validate_depth()
676 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); in evergreen_cs_track_validate_depth()
696 __func__, __LINE__, track->db_depth_size, in evergreen_cs_track_validate_depth()
697 track->db_depth_slice, track->db_z_info); in evergreen_cs_track_validate_depth()
704 __func__, __LINE__, track->db_depth_size, in evergreen_cs_track_validate_depth()
705 track->db_depth_slice, track->db_z_info); in evergreen_cs_track_validate_depth()
709 offset = track->db_z_read_offset << 8; in evergreen_cs_track_validate_depth()
716 if (offset > radeon_bo_size(track->db_z_read_bo)) { in evergreen_cs_track_validate_depth()
720 (unsigned long)track->db_z_read_offset << 8, mslice, in evergreen_cs_track_validate_depth()
721 radeon_bo_size(track->db_z_read_bo)); in evergreen_cs_track_validate_depth()
725 offset = track->db_z_write_offset << 8; in evergreen_cs_track_validate_depth()
732 if (offset > radeon_bo_size(track->db_z_write_bo)) { in evergreen_cs_track_validate_depth()
736 (unsigned long)track->db_z_write_offset << 8, mslice, in evergreen_cs_track_validate_depth()
737 radeon_bo_size(track->db_z_write_bo)); in evergreen_cs_track_validate_depth()
742 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) { in evergreen_cs_track_validate_depth()
933 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_check() local
939 if (track->streamout_dirty && track->vgt_strmout_config) { in evergreen_cs_track_check()
941 if (track->vgt_strmout_config & (1 << i)) { in evergreen_cs_track_check()
942 buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf; in evergreen_cs_track_check()
948 if (track->vgt_strmout_bo[i]) { in evergreen_cs_track_check()
949 u64 offset = (u64)track->vgt_strmout_bo_offset[i] + in evergreen_cs_track_check()
950 (u64)track->vgt_strmout_size[i]; in evergreen_cs_track_check()
951 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { in evergreen_cs_track_check()
954 radeon_bo_size(track->vgt_strmout_bo[i])); in evergreen_cs_track_check()
963 track->streamout_dirty = false; in evergreen_cs_track_check()
966 if (track->sx_misc_kill_all_prims) in evergreen_cs_track_check()
971 if (track->cb_dirty) { in evergreen_cs_track_check()
972 tmp = track->cb_target_mask; in evergreen_cs_track_check()
974 u32 format = G_028C70_FORMAT(track->cb_color_info[i]); in evergreen_cs_track_check()
979 if (track->cb_color_bo[i] == NULL) { in evergreen_cs_track_check()
981 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); in evergreen_cs_track_check()
991 track->cb_dirty = false; in evergreen_cs_track_check()
994 if (track->db_dirty) { in evergreen_cs_track_check()
996 if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID && in evergreen_cs_track_check()
997 G_028800_STENCIL_ENABLE(track->db_depth_control)) { in evergreen_cs_track_check()
1003 if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID && in evergreen_cs_track_check()
1004 G_028800_Z_ENABLE(track->db_depth_control)) { in evergreen_cs_track_check()
1009 track->db_dirty = false; in evergreen_cs_track_check()
1095 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track; in evergreen_cs_handle_reg() local
1151 track->db_depth_control = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1152 track->db_dirty = true; in evergreen_cs_handle_reg()
1169 track->db_z_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1178 track->db_z_info &= ~Z_ARRAY_MODE(0xf); in evergreen_cs_handle_reg()
1180 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1187 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1194 track->db_dirty = true; in evergreen_cs_handle_reg()
1197 track->db_s_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1198 track->db_dirty = true; in evergreen_cs_handle_reg()
1201 track->db_depth_view = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1202 track->db_dirty = true; in evergreen_cs_handle_reg()
1205 track->db_depth_size = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1206 track->db_dirty = true; in evergreen_cs_handle_reg()
1209 track->db_depth_slice = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1210 track->db_dirty = true; in evergreen_cs_handle_reg()
1219 track->db_z_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1221 track->db_z_read_bo = reloc->robj; in evergreen_cs_handle_reg()
1222 track->db_dirty = true; in evergreen_cs_handle_reg()
1231 track->db_z_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1233 track->db_z_write_bo = reloc->robj; in evergreen_cs_handle_reg()
1234 track->db_dirty = true; in evergreen_cs_handle_reg()
1243 track->db_s_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1245 track->db_s_read_bo = reloc->robj; in evergreen_cs_handle_reg()
1246 track->db_dirty = true; in evergreen_cs_handle_reg()
1255 track->db_s_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1257 track->db_s_write_bo = reloc->robj; in evergreen_cs_handle_reg()
1258 track->db_dirty = true; in evergreen_cs_handle_reg()
1261 track->vgt_strmout_config = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1262 track->streamout_dirty = true; in evergreen_cs_handle_reg()
1265 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1266 track->streamout_dirty = true; in evergreen_cs_handle_reg()
1279 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in evergreen_cs_handle_reg()
1281 track->vgt_strmout_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1282 track->streamout_dirty = true; in evergreen_cs_handle_reg()
1290 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in evergreen_cs_handle_reg()
1291 track->streamout_dirty = true; in evergreen_cs_handle_reg()
1303 track->cb_target_mask = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1304 track->cb_dirty = true; in evergreen_cs_handle_reg()
1307 track->cb_shader_mask = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1308 track->cb_dirty = true; in evergreen_cs_handle_reg()
1317 track->nsamples = 1 << tmp; in evergreen_cs_handle_reg()
1326 track->nsamples = 1 << tmp; in evergreen_cs_handle_reg()
1337 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1338 track->cb_dirty = true; in evergreen_cs_handle_reg()
1345 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1346 track->cb_dirty = true; in evergreen_cs_handle_reg()
1357 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1366 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1368 track->cb_dirty = true; in evergreen_cs_handle_reg()
1375 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1384 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1386 track->cb_dirty = true; in evergreen_cs_handle_reg()
1397 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1398 track->cb_dirty = true; in evergreen_cs_handle_reg()
1405 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1406 track->cb_dirty = true; in evergreen_cs_handle_reg()
1417 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1418 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_handle_reg()
1419 track->cb_dirty = true; in evergreen_cs_handle_reg()
1426 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1427 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_handle_reg()
1428 track->cb_dirty = true; in evergreen_cs_handle_reg()
1451 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1459 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1460 track->cb_dirty = true; in evergreen_cs_handle_reg()
1479 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1487 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1488 track->cb_dirty = true; in evergreen_cs_handle_reg()
1505 track->cb_color_fmask_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1522 track->cb_color_cmask_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1533 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1544 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1561 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1563 track->cb_color_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1564 track->cb_dirty = true; in evergreen_cs_handle_reg()
1577 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1579 track->cb_color_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1580 track->cb_dirty = true; in evergreen_cs_handle_reg()
1589 track->htile_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1591 track->htile_bo = reloc->robj; in evergreen_cs_handle_reg()
1592 track->db_dirty = true; in evergreen_cs_handle_reg()
1596 track->htile_surface = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1599 track->db_dirty = true; in evergreen_cs_handle_reg()
1738 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in evergreen_cs_handle_reg()
1757 struct evergreen_cs_track *track = p->track; in evergreen_is_safe_reg() local
1765 if (!(track->reg_safe_bm[i] & m)) in evergreen_is_safe_reg()
1775 struct evergreen_cs_track *track; in evergreen_packet3_check() local
1783 track = (struct evergreen_cs_track *)p->track; in evergreen_packet3_check()
2022 track->indirect_draw_buffer_size = radeon_bo_size(reloc->robj); in evergreen_packet3_check()
2044 if (idx_value + size > track->indirect_draw_buffer_size) { in evergreen_packet3_check()
2046 idx_value, size, track->indirect_draw_buffer_size); in evergreen_packet3_check()
2373 TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_packet3_check()
2674 struct evergreen_cs_track *track; in evergreen_cs_parse() local
2678 if (p->track == NULL) { in evergreen_cs_parse()
2680 track = kzalloc(sizeof(*track), GFP_KERNEL); in evergreen_cs_parse()
2681 if (track == NULL) in evergreen_cs_parse()
2683 evergreen_cs_track_init(track); in evergreen_cs_parse()
2686 track->reg_safe_bm = cayman_reg_safe_bm; in evergreen_cs_parse()
2689 track->reg_safe_bm = evergreen_reg_safe_bm; in evergreen_cs_parse()
2695 track->npipes = 1; in evergreen_cs_parse()
2699 track->npipes = 2; in evergreen_cs_parse()
2702 track->npipes = 4; in evergreen_cs_parse()
2705 track->npipes = 8; in evergreen_cs_parse()
2711 track->nbanks = 4; in evergreen_cs_parse()
2715 track->nbanks = 8; in evergreen_cs_parse()
2718 track->nbanks = 16; in evergreen_cs_parse()
2724 track->group_size = 256; in evergreen_cs_parse()
2728 track->group_size = 512; in evergreen_cs_parse()
2734 track->row_size = 1; in evergreen_cs_parse()
2738 track->row_size = 2; in evergreen_cs_parse()
2741 track->row_size = 4; in evergreen_cs_parse()
2745 p->track = track; in evergreen_cs_parse()
2750 kfree(p->track); in evergreen_cs_parse()
2751 p->track = NULL; in evergreen_cs_parse()
2766 kfree(p->track); in evergreen_cs_parse()
2767 p->track = NULL; in evergreen_cs_parse()
2771 kfree(p->track); in evergreen_cs_parse()
2772 p->track = NULL; in evergreen_cs_parse()
2782 kfree(p->track); in evergreen_cs_parse()
2783 p->track = NULL; in evergreen_cs_parse()