Lines Matching refs:radeon_bo_size
444 if (offset > radeon_bo_size(track->cb_color_bo[id])) { in evergreen_cs_track_validate_cb()
457 bsize = radeon_bo_size(track->cb_color_bo[id]); in evergreen_cs_track_validate_cb()
482 radeon_bo_size(track->cb_color_bo[id]), slice); in evergreen_cs_track_validate_cb()
551 if (size > radeon_bo_size(track->htile_bo)) { in evergreen_cs_track_validate_htile()
553 __func__, __LINE__, radeon_bo_size(track->htile_bo), in evergreen_cs_track_validate_htile()
618 if (offset > radeon_bo_size(track->db_s_read_bo)) { in evergreen_cs_track_validate_stencil()
623 radeon_bo_size(track->db_s_read_bo)); in evergreen_cs_track_validate_stencil()
637 if (offset > radeon_bo_size(track->db_s_write_bo)) { in evergreen_cs_track_validate_stencil()
642 radeon_bo_size(track->db_s_write_bo)); in evergreen_cs_track_validate_stencil()
716 if (offset > radeon_bo_size(track->db_z_read_bo)) { in evergreen_cs_track_validate_depth()
721 radeon_bo_size(track->db_z_read_bo)); in evergreen_cs_track_validate_depth()
732 if (offset > radeon_bo_size(track->db_z_write_bo)) { in evergreen_cs_track_validate_depth()
737 radeon_bo_size(track->db_z_write_bo)); in evergreen_cs_track_validate_depth()
851 if (toffset > radeon_bo_size(texture)) { in evergreen_cs_track_validate_texture()
856 depth, radeon_bo_size(texture), in evergreen_cs_track_validate_texture()
911 if (moffset > radeon_bo_size(mipmap)) { in evergreen_cs_track_validate_texture()
917 d, radeon_bo_size(mipmap), in evergreen_cs_track_validate_texture()
951 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { in evergreen_cs_track_check()
954 radeon_bo_size(track->vgt_strmout_bo[i])); in evergreen_cs_track_check()
2022 track->indirect_draw_buffer_size = radeon_bo_size(reloc->robj); in evergreen_packet3_check()
2159 if ((tmp + size) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2161 tmp + size, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2197 if ((tmp + size) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2199 tmp + size, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2417 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2420 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; in evergreen_packet3_check()
2499 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2501 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2518 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2520 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2547 if ((offset + 8) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2549 offset + 8, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2572 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2574 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2599 if ((offset + 4) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2601 offset + 4, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2847 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2849 dst_offset, radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2872 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
2874 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
2877 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2879 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2912 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
2914 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
2917 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2919 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2931 if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
2933 src_offset + count, radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
2936 if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2938 dst_offset + count, radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2975 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
2977 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
2980 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2982 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2985 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { in evergreen_dma_cs_parse()
2987 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); in evergreen_dma_cs_parse()
3015 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3017 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3020 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3022 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3025 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { in evergreen_dma_cs_parse()
3027 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); in evergreen_dma_cs_parse()
3077 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3079 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3082 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3084 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3087 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { in evergreen_dma_cs_parse()
3089 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); in evergreen_dma_cs_parse()
3123 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3125 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3128 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3130 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3164 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3166 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3169 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3171 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3174 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { in evergreen_dma_cs_parse()
3176 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); in evergreen_dma_cs_parse()
3198 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3200 dst_offset, radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()