2799 	struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc;  in evergreen_dma_cs_parse()  local
2964 				r = r600_dma_cs_next_reloc(p, &dst2_reloc);  in evergreen_dma_cs_parse()
2985 				if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {  in evergreen_dma_cs_parse()
2987 							dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));  in evergreen_dma_cs_parse()
2991 				ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
2994 				ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
3004 				r = r600_dma_cs_next_reloc(p, &dst2_reloc);  in evergreen_dma_cs_parse()
3025 				if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {  in evergreen_dma_cs_parse()
3027 							dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));  in evergreen_dma_cs_parse()
3031 				ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3066 				r = r600_dma_cs_next_reloc(p, &dst2_reloc);  in evergreen_dma_cs_parse()
3087 				if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {  in evergreen_dma_cs_parse()
3089 							dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));  in evergreen_dma_cs_parse()
3093 				ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3153 				r = r600_dma_cs_next_reloc(p, &dst2_reloc);  in evergreen_dma_cs_parse()
3174 				if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {  in evergreen_dma_cs_parse()
3176 							dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));  in evergreen_dma_cs_parse()
3180 				ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()