Lines Matching refs:dst2_offset
2803 u64 src_offset, dst_offset, dst2_offset; in evergreen_dma_cs_parse() local
2971 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2972 dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32; in evergreen_dma_cs_parse()
2985 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { in evergreen_dma_cs_parse()
2987 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); in evergreen_dma_cs_parse()
3011 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3012 dst2_offset <<= 8; in evergreen_dma_cs_parse()
3025 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { in evergreen_dma_cs_parse()
3027 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); in evergreen_dma_cs_parse()
3073 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3074 dst2_offset <<= 8; in evergreen_dma_cs_parse()
3087 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { in evergreen_dma_cs_parse()
3089 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); in evergreen_dma_cs_parse()
3160 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3161 dst2_offset <<= 8; in evergreen_dma_cs_parse()
3174 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { in evergreen_dma_cs_parse()
3176 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); in evergreen_dma_cs_parse()