Lines Matching refs:p
189 static int evergreen_surface_check_linear(struct radeon_cs_parser *p, in evergreen_surface_check_linear() argument
200 static int evergreen_surface_check_linear_aligned(struct radeon_cs_parser *p, in evergreen_surface_check_linear_aligned() argument
204 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_linear_aligned()
214 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", in evergreen_surface_check_linear_aligned()
222 static int evergreen_surface_check_1d(struct radeon_cs_parser *p, in evergreen_surface_check_1d() argument
226 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_1d()
237 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n", in evergreen_surface_check_1d()
245 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n", in evergreen_surface_check_1d()
253 static int evergreen_surface_check_2d(struct radeon_cs_parser *p, in evergreen_surface_check_2d() argument
257 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_2d()
280 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", in evergreen_surface_check_2d()
287 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n", in evergreen_surface_check_2d()
296 static int evergreen_surface_check(struct radeon_cs_parser *p, in evergreen_surface_check() argument
305 return evergreen_surface_check_linear(p, surf, prefix); in evergreen_surface_check()
307 return evergreen_surface_check_linear_aligned(p, surf, prefix); in evergreen_surface_check()
309 return evergreen_surface_check_1d(p, surf, prefix); in evergreen_surface_check()
311 return evergreen_surface_check_2d(p, surf, prefix); in evergreen_surface_check()
313 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n", in evergreen_surface_check()
320 static int evergreen_surface_value_conv_check(struct radeon_cs_parser *p, in evergreen_surface_value_conv_check() argument
332 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n", in evergreen_surface_value_conv_check()
343 dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n", in evergreen_surface_value_conv_check()
353 dev_warn(p->dev, "%s:%d %s invalid bankw %d\n", in evergreen_surface_value_conv_check()
363 dev_warn(p->dev, "%s:%d %s invalid bankh %d\n", in evergreen_surface_value_conv_check()
373 dev_warn(p->dev, "%s:%d %s invalid macro tile aspect %d\n", in evergreen_surface_value_conv_check()
386 dev_warn(p->dev, "%s:%d %s invalid tile split %d\n", in evergreen_surface_value_conv_check()
393 static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned id) in evergreen_cs_track_validate_cb() argument
395 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_cb()
416 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08x)\n", in evergreen_cs_track_validate_cb()
422 r = evergreen_surface_value_conv_check(p, &surf, "cb"); in evergreen_cs_track_validate_cb()
427 r = evergreen_surface_check(p, &surf, "cb"); in evergreen_cs_track_validate_cb()
429 dev_warn(p->dev, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", in evergreen_cs_track_validate_cb()
438 dev_warn(p->dev, "%s:%d cb[%d] bo base %llu not aligned with %ld\n", in evergreen_cs_track_validate_cb()
450 uint32_t *ib = p->ib.ptr; in evergreen_cs_track_validate_cb()
468 if (!evergreen_surface_check(p, &surf, "cb")) { in evergreen_cs_track_validate_cb()
478 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, " in evergreen_cs_track_validate_cb()
483 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n", in evergreen_cs_track_validate_cb()
495 static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p, in evergreen_cs_track_validate_htile() argument
498 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_htile()
502 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n", in evergreen_cs_track_validate_htile()
539 dev_warn(p->dev, "%s:%d invalid num pipes %d\n", in evergreen_cs_track_validate_htile()
552 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n", in evergreen_cs_track_validate_htile()
560 static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p) in evergreen_cs_track_validate_stencil() argument
562 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_stencil()
583 dev_warn(p->dev, "%s:%d stencil invalid format %d\n", in evergreen_cs_track_validate_stencil()
590 r = evergreen_surface_value_conv_check(p, &surf, "stencil"); in evergreen_cs_track_validate_stencil()
595 r = evergreen_surface_check(p, &surf, NULL); in evergreen_cs_track_validate_stencil()
602 r = evergreen_surface_check(p, &surf, "stencil"); in evergreen_cs_track_validate_stencil()
604 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", in evergreen_cs_track_validate_stencil()
613 dev_warn(p->dev, "%s:%d stencil read bo base %llu not aligned with %ld\n", in evergreen_cs_track_validate_stencil()
619 dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, " in evergreen_cs_track_validate_stencil()
624 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", in evergreen_cs_track_validate_stencil()
632 dev_warn(p->dev, "%s:%d stencil write bo base %llu not aligned with %ld\n", in evergreen_cs_track_validate_stencil()
638 dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, " in evergreen_cs_track_validate_stencil()
648 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby); in evergreen_cs_track_validate_stencil()
657 static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p) in evergreen_cs_track_validate_depth() argument
659 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_depth()
688 dev_warn(p->dev, "%s:%d depth invalid format %d\n", in evergreen_cs_track_validate_depth()
693 r = evergreen_surface_value_conv_check(p, &surf, "depth"); in evergreen_cs_track_validate_depth()
695 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n", in evergreen_cs_track_validate_depth()
701 r = evergreen_surface_check(p, &surf, "depth"); in evergreen_cs_track_validate_depth()
703 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n", in evergreen_cs_track_validate_depth()
711 dev_warn(p->dev, "%s:%d stencil read bo base %llu not aligned with %ld\n", in evergreen_cs_track_validate_depth()
717 dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, " in evergreen_cs_track_validate_depth()
727 dev_warn(p->dev, "%s:%d stencil write bo base %llu not aligned with %ld\n", in evergreen_cs_track_validate_depth()
733 dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, " in evergreen_cs_track_validate_depth()
743 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby); in evergreen_cs_track_validate_depth()
752 static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p, in evergreen_cs_track_validate_texture() argument
763 texdw[0] = radeon_get_ib_value(p, idx + 0); in evergreen_cs_track_validate_texture()
764 texdw[1] = radeon_get_ib_value(p, idx + 1); in evergreen_cs_track_validate_texture()
765 texdw[2] = radeon_get_ib_value(p, idx + 2); in evergreen_cs_track_validate_texture()
766 texdw[3] = radeon_get_ib_value(p, idx + 3); in evergreen_cs_track_validate_texture()
767 texdw[4] = radeon_get_ib_value(p, idx + 4); in evergreen_cs_track_validate_texture()
768 texdw[5] = radeon_get_ib_value(p, idx + 5); in evergreen_cs_track_validate_texture()
769 texdw[6] = radeon_get_ib_value(p, idx + 6); in evergreen_cs_track_validate_texture()
770 texdw[7] = radeon_get_ib_value(p, idx + 7); in evergreen_cs_track_validate_texture()
791 if (!r600_fmt_is_valid_texture(surf.format, p->family)) { in evergreen_cs_track_validate_texture()
792 dev_warn(p->dev, "%s:%d texture invalid format %d\n", in evergreen_cs_track_validate_texture()
813 dev_warn(p->dev, "%s:%d texture invalid dimension %d\n", in evergreen_cs_track_validate_texture()
818 r = evergreen_surface_value_conv_check(p, &surf, "texture"); in evergreen_cs_track_validate_texture()
824 evergreen_surface_check(p, &surf, NULL); in evergreen_cs_track_validate_texture()
827 r = evergreen_surface_check(p, &surf, "texture"); in evergreen_cs_track_validate_texture()
829 dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", in evergreen_cs_track_validate_texture()
837 dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n", in evergreen_cs_track_validate_texture()
842 dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n", in evergreen_cs_track_validate_texture()
852 dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, " in evergreen_cs_track_validate_texture()
863 dev_warn(p->dev, "%s:%i got NULL MIP_ADDRESS relocation\n", in evergreen_cs_track_validate_texture()
887 evergreen_surface_check(p, &surf, NULL); in evergreen_cs_track_validate_texture()
894 dev_warn(p->dev, "%s:%d invalid array mode %d\n", in evergreen_cs_track_validate_texture()
901 r = evergreen_surface_check(p, &surf, "mipmap"); in evergreen_cs_track_validate_texture()
912 dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, " in evergreen_cs_track_validate_texture()
919 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n", in evergreen_cs_track_validate_texture()
931 static int evergreen_cs_track_check(struct radeon_cs_parser *p) in evergreen_cs_track_check() argument
933 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_check()
958 dev_warn(p->dev, "No buffer for streamout %d\n", i); in evergreen_cs_track_check()
980 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", in evergreen_cs_track_check()
985 r = evergreen_cs_track_validate_cb(p, i); in evergreen_cs_track_check()
998 r = evergreen_cs_track_validate_stencil(p); in evergreen_cs_track_check()
1005 r = evergreen_cs_track_validate_depth(p); in evergreen_cs_track_check()
1024 static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p) in evergreen_cs_packet_parse_vline() argument
1044 return r600_cs_common_vline_parse(p, vline_start_end, vline_status); in evergreen_cs_packet_parse_vline()
1047 static int evergreen_packet0_check(struct radeon_cs_parser *p, in evergreen_packet0_check() argument
1055 r = evergreen_cs_packet_parse_vline(p); in evergreen_packet0_check()
1069 static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p, in evergreen_cs_parse_packet0() argument
1079 r = evergreen_packet0_check(p, pkt, idx, reg); in evergreen_cs_parse_packet0()
1093 static int evergreen_cs_handle_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) in evergreen_cs_handle_reg() argument
1095 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track; in evergreen_cs_handle_reg()
1100 ib = p->ib.ptr; in evergreen_cs_handle_reg()
1142 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1144 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1151 track->db_depth_control = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1155 if (p->rdev->family < CHIP_CAYMAN) { in evergreen_cs_handle_reg()
1156 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1162 if (p->rdev->family < CHIP_CAYMAN) { in evergreen_cs_handle_reg()
1163 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1169 track->db_z_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1170 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in evergreen_cs_handle_reg()
1171 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1173 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1197 track->db_s_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1201 track->db_depth_view = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1205 track->db_depth_size = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1209 track->db_depth_slice = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1213 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1215 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1219 track->db_z_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1225 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1227 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1231 track->db_z_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1237 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1239 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1243 track->db_s_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1249 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1251 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1255 track->db_s_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1261 track->vgt_strmout_config = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1265 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1272 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1274 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1279 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in evergreen_cs_handle_reg()
1290 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in evergreen_cs_handle_reg()
1294 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1296 dev_warn(p->dev, "missing reloc for CP_COHER_BASE " in evergreen_cs_handle_reg()
1303 track->cb_target_mask = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1307 track->cb_shader_mask = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1311 if (p->rdev->family >= CHIP_CAYMAN) { in evergreen_cs_handle_reg()
1312 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1316 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK; in evergreen_cs_handle_reg()
1320 if (p->rdev->family < CHIP_CAYMAN) { in evergreen_cs_handle_reg()
1321 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1325 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK; in evergreen_cs_handle_reg()
1337 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1345 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1357 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1358 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in evergreen_cs_handle_reg()
1359 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1361 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1375 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1376 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in evergreen_cs_handle_reg()
1377 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1379 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1397 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1405 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1417 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1426 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1438 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1440 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1444 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in evergreen_cs_handle_reg()
1466 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1468 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1472 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in evergreen_cs_handle_reg()
1499 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1501 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); in evergreen_cs_handle_reg()
1516 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1518 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); in evergreen_cs_handle_reg()
1533 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1544 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1554 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1556 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1561 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1570 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1572 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1577 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1583 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1585 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1589 track->htile_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1596 track->htile_surface = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1701 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1703 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1710 if (p->rdev->family >= CHIP_CAYMAN) { in evergreen_cs_handle_reg()
1711 dev_warn(p->dev, "bad SET_CONFIG_REG " in evergreen_cs_handle_reg()
1715 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1717 dev_warn(p->dev, "bad SET_CONFIG_REG " in evergreen_cs_handle_reg()
1724 if (p->rdev->family < CHIP_CAYMAN) { in evergreen_cs_handle_reg()
1725 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1729 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_handle_reg()
1731 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1738 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in evergreen_cs_handle_reg()
1741 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in evergreen_cs_handle_reg()
1755 static inline bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg) in evergreen_is_safe_reg() argument
1757 struct evergreen_cs_track *track = p->track; in evergreen_is_safe_reg()
1771 static int evergreen_packet3_check(struct radeon_cs_parser *p, in evergreen_packet3_check() argument
1783 track = (struct evergreen_cs_track *)p->track; in evergreen_packet3_check()
1784 ib = p->ib.ptr; in evergreen_packet3_check()
1786 idx_value = radeon_get_ib_value(p, idx); in evergreen_packet3_check()
1800 tmp = radeon_get_ib_value(p, idx + 1); in evergreen_packet3_check()
1812 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1841 if (p->rdev->family < CHIP_CAYMAN) { in evergreen_packet3_check()
1858 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1866 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
1871 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
1873 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
1893 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1901 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
1906 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
1908 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
1921 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1928 radeon_get_ib_value(p, idx+1) + in evergreen_packet3_check()
1929 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
1934 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
1936 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
1946 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
1948 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
1957 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
1959 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
1968 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
1970 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
1979 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
1981 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
1990 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
1992 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
2016 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2045 dev_warn(p->dev, "DRAW_INDIRECT buffer too small %u + %llu > %lu\n", in evergreen_packet3_check()
2050 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
2052 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
2062 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
2064 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
2073 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2079 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
2081 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
2094 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2101 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2102 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2119 command = radeon_get_ib_value(p, idx+4); in evergreen_packet3_check()
2121 info = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2148 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2154 tmp = radeon_get_ib_value(p, idx) + in evergreen_packet3_check()
2155 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
2160 dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n", in evergreen_packet3_check()
2186 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2192 tmp = radeon_get_ib_value(p, idx+2) + in evergreen_packet3_check()
2193 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); in evergreen_packet3_check()
2198 dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", in evergreen_packet3_check()
2224 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || in evergreen_packet3_check()
2225 radeon_get_ib_value(p, idx + 2) != 0) { in evergreen_packet3_check()
2226 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2242 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2248 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + in evergreen_packet3_check()
2249 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2263 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2270 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2271 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2285 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2292 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2293 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2309 if (evergreen_is_safe_reg(p, reg)) in evergreen_packet3_check()
2311 r = evergreen_cs_handle_reg(p, reg, idx); in evergreen_packet3_check()
2326 if (evergreen_is_safe_reg(p, reg)) in evergreen_packet3_check()
2328 r = evergreen_cs_handle_reg(p, reg, idx); in evergreen_packet3_check()
2351 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { in evergreen_packet3_check()
2354 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2359 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in evergreen_packet3_check()
2385 !radeon_cs_packet_next_is_pkt3_nop(p)) { in evergreen_packet3_check()
2391 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2400 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8)); in evergreen_packet3_check()
2410 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2415 offset = radeon_get_ib_value(p, idx+1+(i*8)+0); in evergreen_packet3_check()
2416 size = radeon_get_ib_value(p, idx+1+(i*8)+1); in evergreen_packet3_check()
2417 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2419 dev_warn_ratelimited(p->dev, "vbo resource seems too big for the bo\n"); in evergreen_packet3_check()
2492 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2497 offset = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2498 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_packet3_check()
2511 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2516 offset = radeon_get_ib_value(p, idx+3); in evergreen_packet3_check()
2517 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_packet3_check()
2536 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2541 offset = radeon_get_ib_value(p, idx+0); in evergreen_packet3_check()
2542 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; in evergreen_packet3_check()
2565 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2570 offset = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2571 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_packet3_check()
2582 reg = radeon_get_ib_value(p, idx+1) << 2; in evergreen_packet3_check()
2583 if (!evergreen_is_safe_reg(p, reg)) { in evergreen_packet3_check()
2584 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", in evergreen_packet3_check()
2592 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2597 offset = radeon_get_ib_value(p, idx+3); in evergreen_packet3_check()
2598 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_packet3_check()
2609 reg = radeon_get_ib_value(p, idx+3) << 2; in evergreen_packet3_check()
2610 if (!evergreen_is_safe_reg(p, reg)) { in evergreen_packet3_check()
2611 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", in evergreen_packet3_check()
2633 dev_warn(p->dev, "forbidden register for append cnt 0x%08x at %d\n", in evergreen_packet3_check()
2642 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2647 offset = radeon_get_ib_value(p, idx + 1); in evergreen_packet3_check()
2651 offset += ((u64)(radeon_get_ib_value(p, idx + 2) & 0xff)) << 32; in evergreen_packet3_check()
2671 int evergreen_cs_parse(struct radeon_cs_parser *p) in evergreen_cs_parse() argument
2678 if (p->track == NULL) { in evergreen_cs_parse()
2684 if (p->rdev->family >= CHIP_CAYMAN) { in evergreen_cs_parse()
2685 tmp = p->rdev->config.cayman.tile_config; in evergreen_cs_parse()
2688 tmp = p->rdev->config.evergreen.tile_config; in evergreen_cs_parse()
2745 p->track = track; in evergreen_cs_parse()
2748 r = radeon_cs_packet_parse(p, &pkt, p->idx); in evergreen_cs_parse()
2750 kfree(p->track); in evergreen_cs_parse()
2751 p->track = NULL; in evergreen_cs_parse()
2754 p->idx += pkt.count + 2; in evergreen_cs_parse()
2757 r = evergreen_cs_parse_packet0(p, &pkt); in evergreen_cs_parse()
2762 r = evergreen_packet3_check(p, &pkt); in evergreen_cs_parse()
2766 kfree(p->track); in evergreen_cs_parse()
2767 p->track = NULL; in evergreen_cs_parse()
2771 kfree(p->track); in evergreen_cs_parse()
2772 p->track = NULL; in evergreen_cs_parse()
2775 } while (p->idx < p->chunk_ib->length_dw); in evergreen_cs_parse()
2777 for (r = 0; r < p->ib.length_dw; r++) { in evergreen_cs_parse()
2778 pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]); in evergreen_cs_parse()
2782 kfree(p->track); in evergreen_cs_parse()
2783 p->track = NULL; in evergreen_cs_parse()
2796 int evergreen_dma_cs_parse(struct radeon_cs_parser *p) in evergreen_dma_cs_parse() argument
2798 struct radeon_cs_chunk *ib_chunk = p->chunk_ib; in evergreen_dma_cs_parse()
2801 uint32_t *ib = p->ib.ptr; in evergreen_dma_cs_parse()
2807 if (p->idx >= ib_chunk->length_dw) { in evergreen_dma_cs_parse()
2809 p->idx, ib_chunk->length_dw); in evergreen_dma_cs_parse()
2812 idx = p->idx; in evergreen_dma_cs_parse()
2813 header = radeon_get_ib_value(p, idx); in evergreen_dma_cs_parse()
2820 r = r600_dma_cs_next_reloc(p, &dst_reloc); in evergreen_dma_cs_parse()
2828 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2832 p->idx += count + 7; in evergreen_dma_cs_parse()
2836 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2837 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_dma_cs_parse()
2841 p->idx += count + 3; in evergreen_dma_cs_parse()
2848 dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2854 r = r600_dma_cs_next_reloc(p, &src_reloc); in evergreen_dma_cs_parse()
2859 r = r600_dma_cs_next_reloc(p, &dst_reloc); in evergreen_dma_cs_parse()
2868 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2869 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2870 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2871 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2873 dev_warn(p->dev, "DMA L2L, dw src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2878 dev_warn(p->dev, "DMA L2L, dw dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2886 p->idx += 5; in evergreen_dma_cs_parse()
2891 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
2893 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2897 dst_offset = radeon_get_ib_value(p, idx + 7); in evergreen_dma_cs_parse()
2898 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2903 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
2904 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2908 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2913 dev_warn(p->dev, "DMA L2T, src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2918 dev_warn(p->dev, "DMA L2T, dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2922 p->idx += 9; in evergreen_dma_cs_parse()
2927 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2928 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2929 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2930 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2932 dev_warn(p->dev, "DMA L2L, byte src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2937 dev_warn(p->dev, "DMA L2L, byte dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2945 p->idx += 5; in evergreen_dma_cs_parse()
2950 if (p->family < CHIP_CAYMAN) { in evergreen_dma_cs_parse()
2959 p->idx += 9; in evergreen_dma_cs_parse()
2964 r = r600_dma_cs_next_reloc(p, &dst2_reloc); in evergreen_dma_cs_parse()
2969 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2970 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2971 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2972 dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32; in evergreen_dma_cs_parse()
2973 src_offset = radeon_get_ib_value(p, idx+3); in evergreen_dma_cs_parse()
2974 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in evergreen_dma_cs_parse()
2976 dev_warn(p->dev, "DMA L2L, dw, broadcast src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2981 dev_warn(p->dev, "DMA L2L, dw, broadcast dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2986 dev_warn(p->dev, "DMA L2L, dw, broadcast dst2 buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2996 p->idx += 7; in evergreen_dma_cs_parse()
3000 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3004 r = r600_dma_cs_next_reloc(p, &dst2_reloc); in evergreen_dma_cs_parse()
3009 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3011 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3013 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3014 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3016 dev_warn(p->dev, "DMA L2T, frame to fields src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3021 dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3026 dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3034 p->idx += 10; in evergreen_dma_cs_parse()
3039 if (p->family < CHIP_CAYMAN) { in evergreen_dma_cs_parse()
3044 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3057 p->idx += 12; in evergreen_dma_cs_parse()
3062 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3066 r = r600_dma_cs_next_reloc(p, &dst2_reloc); in evergreen_dma_cs_parse()
3071 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3073 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3075 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3076 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3078 dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3083 dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3088 dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3096 p->idx += 10; in evergreen_dma_cs_parse()
3102 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3104 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3108 dst_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3109 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3114 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3115 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3119 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3124 dev_warn(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3129 dev_warn(p->dev, "DMA L2T, T2L dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3133 p->idx += 9; in evergreen_dma_cs_parse()
3138 if (p->family < CHIP_CAYMAN) { in evergreen_dma_cs_parse()
3144 p->idx += 13; in evergreen_dma_cs_parse()
3149 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3153 r = r600_dma_cs_next_reloc(p, &dst2_reloc); in evergreen_dma_cs_parse()
3158 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3160 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3162 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3163 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3165 dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3170 dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3175 dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3183 p->idx += 10; in evergreen_dma_cs_parse()
3191 r = r600_dma_cs_next_reloc(p, &dst_reloc); in evergreen_dma_cs_parse()
3196 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3197 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; in evergreen_dma_cs_parse()
3199 dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3205 p->idx += 4; in evergreen_dma_cs_parse()
3208 p->idx += 1; in evergreen_dma_cs_parse()
3214 } while (p->idx < p->chunk_ib->length_dw); in evergreen_dma_cs_parse()
3216 for (r = 0; r < p->ib->length_dw; r++) { in evergreen_dma_cs_parse()
3217 pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]); in evergreen_dma_cs_parse()