Lines Matching refs:idx
755 unsigned idx) in evergreen_cs_track_validate_texture() argument
763 texdw[0] = radeon_get_ib_value(p, idx + 0); in evergreen_cs_track_validate_texture()
764 texdw[1] = radeon_get_ib_value(p, idx + 1); in evergreen_cs_track_validate_texture()
765 texdw[2] = radeon_get_ib_value(p, idx + 2); in evergreen_cs_track_validate_texture()
766 texdw[3] = radeon_get_ib_value(p, idx + 3); in evergreen_cs_track_validate_texture()
767 texdw[4] = radeon_get_ib_value(p, idx + 4); in evergreen_cs_track_validate_texture()
768 texdw[5] = radeon_get_ib_value(p, idx + 5); in evergreen_cs_track_validate_texture()
769 texdw[6] = radeon_get_ib_value(p, idx + 6); in evergreen_cs_track_validate_texture()
770 texdw[7] = radeon_get_ib_value(p, idx + 7); in evergreen_cs_track_validate_texture()
1049 unsigned idx, unsigned reg) in evergreen_packet0_check() argument
1058 idx, reg); in evergreen_packet0_check()
1063 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx); in evergreen_packet0_check()
1073 unsigned idx; in evergreen_cs_parse_packet0() local
1076 idx = pkt->idx + 1; in evergreen_cs_parse_packet0()
1078 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { in evergreen_cs_parse_packet0()
1079 r = evergreen_packet0_check(p, pkt, idx, reg); in evergreen_cs_parse_packet0()
1093 static int evergreen_cs_handle_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) in evergreen_cs_handle_reg() argument
1148 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1151 track->db_depth_control = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1169 track->db_z_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1177 ib[idx] &= ~Z_ARRAY_MODE(0xf); in evergreen_cs_handle_reg()
1179 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1187 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1188 ib[idx] |= DB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1197 track->db_s_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1201 track->db_depth_view = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1205 track->db_depth_size = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1209 track->db_depth_slice = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1219 track->db_z_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1220 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1231 track->db_z_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1232 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1243 track->db_s_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1244 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1255 track->db_s_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1256 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1261 track->vgt_strmout_config = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1265 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1279 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in evergreen_cs_handle_reg()
1280 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1290 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in evergreen_cs_handle_reg()
1300 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1303 track->cb_target_mask = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1307 track->cb_shader_mask = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1316 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK; in evergreen_cs_handle_reg()
1325 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK; in evergreen_cs_handle_reg()
1337 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1345 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1357 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1365 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1375 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1383 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1397 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1405 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1417 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1418 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_handle_reg()
1426 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1427 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_handle_reg()
1451 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1452 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1459 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1479 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1480 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1487 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1504 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1521 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1533 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1544 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1561 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1562 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1577 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1578 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1589 track->htile_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1590 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1596 track->htile_surface = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1598 ib[idx] |= 3; in evergreen_cs_handle_reg()
1707 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1721 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1735 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1738 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in evergreen_cs_handle_reg()
1741 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in evergreen_cs_handle_reg()
1777 unsigned idx; in evergreen_packet3_check() local
1785 idx = pkt->idx + 1; in evergreen_packet3_check()
1786 idx_value = radeon_get_ib_value(p, idx); in evergreen_packet3_check()
1800 tmp = radeon_get_ib_value(p, idx + 1); in evergreen_packet3_check()
1822 ib[idx + 0] = offset; in evergreen_packet3_check()
1823 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
1866 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
1868 ib[idx+0] = offset; in evergreen_packet3_check()
1869 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1901 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
1903 ib[idx+0] = offset; in evergreen_packet3_check()
1904 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1928 radeon_get_ib_value(p, idx+1) + in evergreen_packet3_check()
1929 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
1931 ib[idx+1] = offset; in evergreen_packet3_check()
1932 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1948 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
1959 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
2024 ib[idx+1] = reloc->gpu_offset; in evergreen_packet3_check()
2025 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; in evergreen_packet3_check()
2064 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
2078 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2101 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2102 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2104 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc); in evergreen_packet3_check()
2105 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2119 command = radeon_get_ib_value(p, idx+4); in evergreen_packet3_check()
2121 info = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2154 tmp = radeon_get_ib_value(p, idx) + in evergreen_packet3_check()
2155 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
2165 ib[idx] = offset; in evergreen_packet3_check()
2166 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2192 tmp = radeon_get_ib_value(p, idx+2) + in evergreen_packet3_check()
2193 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); in evergreen_packet3_check()
2203 ib[idx+2] = offset; in evergreen_packet3_check()
2204 ib[idx+3] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2224 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || in evergreen_packet3_check()
2225 radeon_get_ib_value(p, idx + 2) != 0) { in evergreen_packet3_check()
2231 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2248 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + in evergreen_packet3_check()
2249 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2251 ib[idx+1] = offset & 0xfffffff8; in evergreen_packet3_check()
2252 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2270 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2271 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2273 ib[idx+1] = offset & 0xfffffffc; in evergreen_packet3_check()
2274 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2292 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2293 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2295 ib[idx+1] = offset & 0xfffffffc; in evergreen_packet3_check()
2296 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2308 for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) { in evergreen_packet3_check()
2311 r = evergreen_cs_handle_reg(p, reg, idx); in evergreen_packet3_check()
2325 for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) { in evergreen_packet3_check()
2328 r = evergreen_cs_handle_reg(p, reg, idx); in evergreen_packet3_check()
2351 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { in evergreen_packet3_check()
2360 ib[idx+1+(i*8)+1] |= in evergreen_packet3_check()
2368 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split); in evergreen_packet3_check()
2369 ib[idx+1+(i*8)+7] |= in evergreen_packet3_check()
2380 tex_dim = ib[idx+1+(i*8)+0] & 0x7; in evergreen_packet3_check()
2381 mip_address = ib[idx+1+(i*8)+3]; in evergreen_packet3_check()
2400 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8)); in evergreen_packet3_check()
2403 ib[idx+1+(i*8)+2] += toffset; in evergreen_packet3_check()
2404 ib[idx+1+(i*8)+3] += moffset; in evergreen_packet3_check()
2415 offset = radeon_get_ib_value(p, idx+1+(i*8)+0); in evergreen_packet3_check()
2416 size = radeon_get_ib_value(p, idx+1+(i*8)+1); in evergreen_packet3_check()
2420 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; in evergreen_packet3_check()
2424 ib[idx+1+(i*8)+0] = offset64; in evergreen_packet3_check()
2425 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | in evergreen_packet3_check()
2497 offset = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2498 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_packet3_check()
2505 ib[idx+1] = offset; in evergreen_packet3_check()
2506 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2516 offset = radeon_get_ib_value(p, idx+3); in evergreen_packet3_check()
2517 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_packet3_check()
2524 ib[idx+3] = offset; in evergreen_packet3_check()
2525 ib[idx+4] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2541 offset = radeon_get_ib_value(p, idx+0); in evergreen_packet3_check()
2542 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; in evergreen_packet3_check()
2553 ib[idx+0] = offset; in evergreen_packet3_check()
2554 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2570 offset = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2571 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_packet3_check()
2578 ib[idx+1] = offset; in evergreen_packet3_check()
2579 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2582 reg = radeon_get_ib_value(p, idx+1) << 2; in evergreen_packet3_check()
2585 reg, idx + 1); in evergreen_packet3_check()
2597 offset = radeon_get_ib_value(p, idx+3); in evergreen_packet3_check()
2598 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_packet3_check()
2605 ib[idx+3] = offset; in evergreen_packet3_check()
2606 ib[idx+4] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2609 reg = radeon_get_ib_value(p, idx+3) << 2; in evergreen_packet3_check()
2612 reg, idx + 3); in evergreen_packet3_check()
2634 areg, idx); in evergreen_packet3_check()
2647 offset = radeon_get_ib_value(p, idx + 1); in evergreen_packet3_check()
2651 offset += ((u64)(radeon_get_ib_value(p, idx + 2) & 0xff)) << 32; in evergreen_packet3_check()
2654 ib[idx+1] = (offset & 0xfffffffc) | swap; in evergreen_packet3_check()
2655 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2748 r = radeon_cs_packet_parse(p, &pkt, p->idx); in evergreen_cs_parse()
2754 p->idx += pkt.count + 2; in evergreen_cs_parse()
2775 } while (p->idx < p->chunk_ib->length_dw); in evergreen_cs_parse()
2802 u32 idx; in evergreen_dma_cs_parse() local
2807 if (p->idx >= ib_chunk->length_dw) { in evergreen_dma_cs_parse()
2809 p->idx, ib_chunk->length_dw); in evergreen_dma_cs_parse()
2812 idx = p->idx; in evergreen_dma_cs_parse()
2813 header = radeon_get_ib_value(p, idx); in evergreen_dma_cs_parse()
2828 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2831 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2832 p->idx += count + 7; in evergreen_dma_cs_parse()
2836 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2837 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_dma_cs_parse()
2839 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2840 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2841 p->idx += count + 3; in evergreen_dma_cs_parse()
2844 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, header); in evergreen_dma_cs_parse()
2868 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2869 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2870 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2871 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2882 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2883 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2884 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2885 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2886 p->idx += 5; in evergreen_dma_cs_parse()
2891 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
2893 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2895 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2897 dst_offset = radeon_get_ib_value(p, idx + 7); in evergreen_dma_cs_parse()
2898 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2899 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2900 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2903 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
2904 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2905 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2906 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2908 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2910 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2922 p->idx += 9; in evergreen_dma_cs_parse()
2927 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2928 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2929 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2930 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2941 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2942 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2943 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2944 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2945 p->idx += 5; in evergreen_dma_cs_parse()
2954 ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2955 ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2956 ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2957 ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2959 p->idx += 9; in evergreen_dma_cs_parse()
2969 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2970 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2971 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2972 dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32; in evergreen_dma_cs_parse()
2973 src_offset = radeon_get_ib_value(p, idx+3); in evergreen_dma_cs_parse()
2974 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in evergreen_dma_cs_parse()
2990 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2991 ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2992 ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2993 ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2994 ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2995 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2996 p->idx += 7; in evergreen_dma_cs_parse()
3000 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3009 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3011 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3013 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3014 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3030 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3031 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3032 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3033 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3034 p->idx += 10; in evergreen_dma_cs_parse()
3044 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3046 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3048 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3049 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3052 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3053 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3055 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3057 p->idx += 12; in evergreen_dma_cs_parse()
3062 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3071 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3073 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3075 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3076 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3092 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3093 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3094 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3095 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3096 p->idx += 10; in evergreen_dma_cs_parse()
3102 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3104 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3106 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3108 dst_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3109 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3110 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3111 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3114 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3115 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3116 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3117 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3119 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3121 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3133 p->idx += 9; in evergreen_dma_cs_parse()
3142 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3143 ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3144 p->idx += 13; in evergreen_dma_cs_parse()
3149 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3158 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3160 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3162 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3163 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3179 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3180 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3181 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3182 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3183 p->idx += 10; in evergreen_dma_cs_parse()
3186 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, header); in evergreen_dma_cs_parse()
3196 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3197 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; in evergreen_dma_cs_parse()
3203 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3204 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; in evergreen_dma_cs_parse()
3205 p->idx += 4; in evergreen_dma_cs_parse()
3208 p->idx += 1; in evergreen_dma_cs_parse()
3211 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); in evergreen_dma_cs_parse()
3214 } while (p->idx < p->chunk_ib->length_dw); in evergreen_dma_cs_parse()
3350 u32 idx = pkt->idx + 1; in evergreen_vm_packet3_check() local
3351 u32 idx_value = ib[idx]; in evergreen_vm_packet3_check()
3408 reg = ib[idx + 5] * 4; in evergreen_vm_packet3_check()
3415 reg = ib[idx + 3] * 4; in evergreen_vm_packet3_check()
3436 command = ib[idx + 4]; in evergreen_vm_packet3_check()
3437 info = ib[idx + 1]; in evergreen_vm_packet3_check()
3474 start_reg = ib[idx + 2]; in evergreen_vm_packet3_check()
3509 areg, idx); in evergreen_vm_packet3_check()
3523 u32 idx = 0; in evergreen_ib_parse() local
3527 pkt.idx = idx; in evergreen_ib_parse()
3528 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]); in evergreen_ib_parse()
3529 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]); in evergreen_ib_parse()
3537 idx += 1; in evergreen_ib_parse()
3540 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]); in evergreen_ib_parse()
3542 idx += pkt.count + 2; in evergreen_ib_parse()
3551 } while (idx < ib->length_dw); in evergreen_ib_parse()
3567 u32 idx = 0; in evergreen_dma_ib_parse() local
3571 header = ib->ptr[idx]; in evergreen_dma_ib_parse()
3581 idx += count + 7; in evergreen_dma_ib_parse()
3585 idx += count + 3; in evergreen_dma_ib_parse()
3588 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, ib->ptr[idx]); in evergreen_dma_ib_parse()
3596 idx += 5; in evergreen_dma_ib_parse()
3600 idx += 9; in evergreen_dma_ib_parse()
3604 idx += 5; in evergreen_dma_ib_parse()
3608 idx += 9; in evergreen_dma_ib_parse()
3612 idx += 7; in evergreen_dma_ib_parse()
3616 idx += 10; in evergreen_dma_ib_parse()
3620 idx += 12; in evergreen_dma_ib_parse()
3624 idx += 10; in evergreen_dma_ib_parse()
3628 idx += 9; in evergreen_dma_ib_parse()
3632 idx += 13; in evergreen_dma_ib_parse()
3636 idx += 10; in evergreen_dma_ib_parse()
3639 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, ib->ptr[idx]); in evergreen_dma_ib_parse()
3644 idx += 4; in evergreen_dma_ib_parse()
3647 idx += 1; in evergreen_dma_ib_parse()
3650 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); in evergreen_dma_ib_parse()
3653 } while (idx < ib->length_dw); in evergreen_dma_ib_parse()