Lines Matching refs:WREG32
185 WREG32(CIK_DIDT_IND_INDEX, (reg)); in cik_didt_rreg()
196 WREG32(CIK_DIDT_IND_INDEX, (reg)); in cik_didt_wreg()
197 WREG32(CIK_DIDT_IND_DATA, (v)); in cik_didt_wreg()
243 WREG32(PCIE_INDEX, reg); in cik_pciep_rreg()
255 WREG32(PCIE_INDEX, reg); in cik_pciep_wreg()
257 WREG32(PCIE_DATA, v); in cik_pciep_wreg()
1848 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl); in cik_srbm_select()
1906 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ci_mc_load_microcode()
1907 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in ci_mc_load_microcode()
1912 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in ci_mc_load_microcode()
1913 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); in ci_mc_load_microcode()
1915 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); in ci_mc_load_microcode()
1916 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); in ci_mc_load_microcode()
1922 WREG32(MC_SEQ_IO_DEBUG_INDEX, 5); in ci_mc_load_microcode()
1923 WREG32(MC_SEQ_IO_DEBUG_DATA, 0x00000023); in ci_mc_load_microcode()
1924 WREG32(MC_SEQ_IO_DEBUG_INDEX, 9); in ci_mc_load_microcode()
1925 WREG32(MC_SEQ_IO_DEBUG_DATA, 0x000001f0); in ci_mc_load_microcode()
1931 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); in ci_mc_load_microcode()
1933 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); in ci_mc_load_microcode()
1937 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ci_mc_load_microcode()
1938 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); in ci_mc_load_microcode()
1939 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); in ci_mc_load_microcode()
2494 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in cik_tiling_mode_table_init()
2496 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); in cik_tiling_mode_table_init()
2637 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in cik_tiling_mode_table_init()
2639 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); in cik_tiling_mode_table_init()
2862 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in cik_tiling_mode_table_init()
2864 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); in cik_tiling_mode_table_init()
3005 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in cik_tiling_mode_table_init()
3007 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); in cik_tiling_mode_table_init()
3039 WREG32(GRBM_GFX_INDEX, data); in cik_select_se_sh()
3155 WREG32(PA_SC_RASTER_CONFIG, data); in cik_setup_rb()
3251 WREG32((0x2c14 + j), 0x00000000); in cik_gpu_init()
3252 WREG32((0x2c18 + j), 0x00000000); in cik_gpu_init()
3253 WREG32((0x2c1c + j), 0x00000000); in cik_gpu_init()
3254 WREG32((0x2c20 + j), 0x00000000); in cik_gpu_init()
3255 WREG32((0x2c24 + j), 0x00000000); in cik_gpu_init()
3258 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in cik_gpu_init()
3259 WREG32(SRBM_INT_CNTL, 0x1); in cik_gpu_init()
3260 WREG32(SRBM_INT_ACK, 0x1); in cik_gpu_init()
3262 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); in cik_gpu_init()
3324 WREG32(GB_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3325 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3326 WREG32(DMIF_ADDR_CALC, gb_addr_config); in cik_gpu_init()
3327 WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
3328 WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
3329 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3330 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3331 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3348 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); in cik_gpu_init()
3350 WREG32(SX_DEBUG_1, 0x20); in cik_gpu_init()
3352 WREG32(TA_CNTL_AUX, 0x00010000); in cik_gpu_init()
3356 WREG32(SPI_CONFIG_CNTL, tmp); in cik_gpu_init()
3358 WREG32(SQ_CONFIG, 1); in cik_gpu_init()
3360 WREG32(DB_DEBUG, 0); in cik_gpu_init()
3364 WREG32(DB_DEBUG2, tmp); in cik_gpu_init()
3368 WREG32(DB_DEBUG3, tmp); in cik_gpu_init()
3372 WREG32(CB_HW_CONTROL, tmp); in cik_gpu_init()
3374 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); in cik_gpu_init()
3376 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) | in cik_gpu_init()
3381 WREG32(VGT_NUM_INSTANCES, 1); in cik_gpu_init()
3383 WREG32(CP_PERFMON_CNTL, 0); in cik_gpu_init()
3385 WREG32(SQ_CONFIG, 0); in cik_gpu_init()
3387 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | in cik_gpu_init()
3390 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | in cik_gpu_init()
3393 WREG32(VGT_GS_VERTEX_REUSE, 16); in cik_gpu_init()
3394 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in cik_gpu_init()
3398 WREG32(HDP_MISC_CNTL, tmp); in cik_gpu_init()
3401 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); in cik_gpu_init()
3403 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); in cik_gpu_init()
3404 WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER); in cik_gpu_init()
3457 WREG32(scratch, 0xCAFEDEAD); in cik_ring_test()
3782 WREG32(scratch, 0xCAFEDEAD); in cik_ib_test()
3866 WREG32(CP_ME_CNTL, 0); in cik_cp_gfx_enable()
3870 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in cik_cp_gfx_enable()
3911 WREG32(CP_PFP_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3913 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3914 WREG32(CP_PFP_UCODE_ADDR, le32_to_cpu(pfp_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
3920 WREG32(CP_CE_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3922 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3923 WREG32(CP_CE_UCODE_ADDR, le32_to_cpu(ce_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
3929 WREG32(CP_ME_RAM_WADDR, 0); in cik_cp_gfx_load_microcode()
3931 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3932 WREG32(CP_ME_RAM_WADDR, le32_to_cpu(me_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
3933 WREG32(CP_ME_RAM_RADDR, le32_to_cpu(me_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
3939 WREG32(CP_PFP_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3941 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3942 WREG32(CP_PFP_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3946 WREG32(CP_CE_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3948 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3949 WREG32(CP_CE_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3953 WREG32(CP_ME_RAM_WADDR, 0); in cik_cp_gfx_load_microcode()
3955 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3956 WREG32(CP_ME_RAM_WADDR, 0); in cik_cp_gfx_load_microcode()
3977 WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1); in cik_cp_gfx_start()
3978 WREG32(CP_ENDIAN_SWAP, 0); in cik_cp_gfx_start()
3979 WREG32(CP_DEVICE_ID, 1); in cik_cp_gfx_start()
4054 WREG32(CP_SEM_WAIT_TIMER, 0x0); in cik_cp_gfx_resume()
4056 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in cik_cp_gfx_resume()
4059 WREG32(CP_RB_WPTR_DELAY, 0); in cik_cp_gfx_resume()
4062 WREG32(CP_RB_VMID, 0); in cik_cp_gfx_resume()
4064 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in cik_cp_gfx_resume()
4074 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4077 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in cik_cp_gfx_resume()
4079 WREG32(CP_RB0_WPTR, ring->wptr); in cik_cp_gfx_resume()
4082 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); in cik_cp_gfx_resume()
4083 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in cik_cp_gfx_resume()
4086 WREG32(SCRATCH_UMSK, 0); in cik_cp_gfx_resume()
4092 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4095 WREG32(CP_RB0_BASE, rb_addr); in cik_cp_gfx_resume()
4096 WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr)); in cik_cp_gfx_resume()
4135 WREG32(CP_RB0_WPTR, ring->wptr); in cik_gfx_set_wptr()
4193 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); in cik_compute_stop()
4196 WREG32(CP_HQD_DEQUEUE_REQUEST, 1); in cik_compute_stop()
4202 WREG32(CP_HQD_DEQUEUE_REQUEST, 0); in cik_compute_stop()
4203 WREG32(CP_HQD_PQ_RPTR, 0); in cik_compute_stop()
4204 WREG32(CP_HQD_PQ_WPTR, 0); in cik_compute_stop()
4220 WREG32(CP_MEC_CNTL, 0); in cik_cp_compute_enable()
4231 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT)); in cik_cp_compute_enable()
4267 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4269 WREG32(CP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4270 WREG32(CP_MEC_ME1_UCODE_ADDR, le32_to_cpu(mec_hdr->header.ucode_version)); in cik_cp_compute_load_microcode()
4281 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4283 WREG32(CP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4284 WREG32(CP_MEC_ME2_UCODE_ADDR, le32_to_cpu(mec2_hdr->header.ucode_version)); in cik_cp_compute_load_microcode()
4291 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4293 WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4294 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4299 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4301 WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4302 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4527 WREG32(CP_CPF_DEBUG, tmp); in cik_cp_compute_resume()
4540 WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); in cik_cp_compute_resume()
4541 WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); in cik_cp_compute_resume()
4544 WREG32(CP_HPD_EOP_VMID, 0); in cik_cp_compute_resume()
4550 WREG32(CP_HPD_EOP_CONTROL, tmp); in cik_cp_compute_resume()
4612 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); in cik_cp_compute_resume()
4621 WREG32(CP_HQD_PQ_DOORBELL_CONTROL, in cik_cp_compute_resume()
4629 WREG32(CP_HQD_DEQUEUE_REQUEST, 1); in cik_cp_compute_resume()
4635 WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request); in cik_cp_compute_resume()
4636 WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr); in cik_cp_compute_resume()
4637 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); in cik_cp_compute_resume()
4643 WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr); in cik_cp_compute_resume()
4644 WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi); in cik_cp_compute_resume()
4648 WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control); in cik_cp_compute_resume()
4654 WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base); in cik_cp_compute_resume()
4655 WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi); in cik_cp_compute_resume()
4673 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); in cik_cp_compute_resume()
4682 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr); in cik_cp_compute_resume()
4683 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR_HI, in cik_cp_compute_resume()
4694 WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR, in cik_cp_compute_resume()
4696 WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR_HI, in cik_cp_compute_resume()
4713 WREG32(CP_HQD_PQ_DOORBELL_CONTROL, in cik_cp_compute_resume()
4719 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); in cik_cp_compute_resume()
4724 WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid); in cik_cp_compute_resume()
4728 WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active); in cik_cp_compute_resume()
4947 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_soft_reset()
4950 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); in cik_gpu_soft_reset()
4956 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
4962 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
5012 WREG32(GRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5018 WREG32(GRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5026 WREG32(SRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5032 WREG32(SRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5058 WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP); in kv_save_regs_for_reset()
5059 WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE | in kv_save_regs_for_reset()
5068 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5069 WREG32(GMCON_PGFSM_CONFIG, 0x200010ff); in kv_restore_regs_for_reset()
5072 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5074 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5075 WREG32(GMCON_PGFSM_CONFIG, 0x300010ff); in kv_restore_regs_for_reset()
5078 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5080 WREG32(GMCON_PGFSM_WRITE, 0x210000); in kv_restore_regs_for_reset()
5081 WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff); in kv_restore_regs_for_reset()
5084 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5086 WREG32(GMCON_PGFSM_WRITE, 0x21003); in kv_restore_regs_for_reset()
5087 WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff); in kv_restore_regs_for_reset()
5090 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5092 WREG32(GMCON_PGFSM_WRITE, 0x2b00); in kv_restore_regs_for_reset()
5093 WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff); in kv_restore_regs_for_reset()
5096 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5098 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5099 WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff); in kv_restore_regs_for_reset()
5102 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5104 WREG32(GMCON_PGFSM_WRITE, 0x420000); in kv_restore_regs_for_reset()
5105 WREG32(GMCON_PGFSM_CONFIG, 0x100010ff); in kv_restore_regs_for_reset()
5108 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5110 WREG32(GMCON_PGFSM_WRITE, 0x120202); in kv_restore_regs_for_reset()
5111 WREG32(GMCON_PGFSM_CONFIG, 0x500010ff); in kv_restore_regs_for_reset()
5114 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5116 WREG32(GMCON_PGFSM_WRITE, 0x3e3e36); in kv_restore_regs_for_reset()
5117 WREG32(GMCON_PGFSM_CONFIG, 0x600010ff); in kv_restore_regs_for_reset()
5120 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5122 WREG32(GMCON_PGFSM_WRITE, 0x373f3e); in kv_restore_regs_for_reset()
5123 WREG32(GMCON_PGFSM_CONFIG, 0x700010ff); in kv_restore_regs_for_reset()
5126 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5128 WREG32(GMCON_PGFSM_WRITE, 0x3e1332); in kv_restore_regs_for_reset()
5129 WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff); in kv_restore_regs_for_reset()
5131 WREG32(GMCON_MISC3, save->gmcon_misc3); in kv_restore_regs_for_reset()
5132 WREG32(GMCON_MISC, save->gmcon_misc); in kv_restore_regs_for_reset()
5133 WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute); in kv_restore_regs_for_reset()
5151 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_pci_config_reset()
5154 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); in cik_gpu_pci_config_reset()
5159 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5163 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5279 WREG32((0x2c14 + j), 0x00000000); in cik_mc_program()
5280 WREG32((0x2c18 + j), 0x00000000); in cik_mc_program()
5281 WREG32((0x2c1c + j), 0x00000000); in cik_mc_program()
5282 WREG32((0x2c20 + j), 0x00000000); in cik_mc_program()
5283 WREG32((0x2c24 + j), 0x00000000); in cik_mc_program()
5285 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); in cik_mc_program()
5292 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in cik_mc_program()
5294 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in cik_mc_program()
5296 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in cik_mc_program()
5298 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, in cik_mc_program()
5302 WREG32(MC_VM_FB_LOCATION, tmp); in cik_mc_program()
5304 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in cik_mc_program()
5305 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); in cik_mc_program()
5306 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); in cik_mc_program()
5307 WREG32(MC_VM_AGP_BASE, 0); in cik_mc_program()
5308 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); in cik_mc_program()
5309 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); in cik_mc_program()
5402 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0); in cik_pcie_gart_tlb_flush()
5405 WREG32(VM_INVALIDATE_REQUEST, 0x1); in cik_pcie_gart_tlb_flush()
5431 WREG32(MC_VM_MX_L1_TLB_CNTL, in cik_pcie_gart_enable()
5439 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cik_pcie_gart_enable()
5445 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable()
5446 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_enable()
5450 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in cik_pcie_gart_enable()
5451 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in cik_pcie_gart_enable()
5452 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cik_pcie_gart_enable()
5453 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in cik_pcie_gart_enable()
5455 WREG32(VM_CONTEXT0_CNTL2, 0); in cik_pcie_gart_enable()
5456 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cik_pcie_gart_enable()
5459 WREG32(0x15D4, 0); in cik_pcie_gart_enable()
5460 WREG32(0x15D8, 0); in cik_pcie_gart_enable()
5461 WREG32(0x15DC, 0); in cik_pcie_gart_enable()
5465 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); in cik_pcie_gart_enable()
5466 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1); in cik_pcie_gart_enable()
5469 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), in cik_pcie_gart_enable()
5472 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), in cik_pcie_gart_enable()
5477 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, in cik_pcie_gart_enable()
5479 WREG32(VM_CONTEXT1_CNTL2, 4); in cik_pcie_gart_enable()
5480 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cik_pcie_gart_enable()
5498 WREG32(CHUB_CONTROL, tmp); in cik_pcie_gart_enable()
5507 WREG32(SH_MEM_CONFIG, SH_MEM_CONFIG_GFX_DEFAULT); in cik_pcie_gart_enable()
5508 WREG32(SH_MEM_APE1_BASE, 1); in cik_pcie_gart_enable()
5509 WREG32(SH_MEM_APE1_LIMIT, 0); in cik_pcie_gart_enable()
5510 WREG32(SH_MEM_BASES, 0); in cik_pcie_gart_enable()
5512 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5513 WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5514 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5515 WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5550 WREG32(VM_CONTEXT0_CNTL, 0); in cik_pcie_gart_disable()
5551 WREG32(VM_CONTEXT1_CNTL, 0); in cik_pcie_gart_disable()
5553 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | in cik_pcie_gart_disable()
5556 WREG32(VM_L2_CNTL, in cik_pcie_gart_disable()
5562 WREG32(VM_L2_CNTL2, 0); in cik_pcie_gart_disable()
5563 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_disable()
5766 WREG32(CP_INT_CNTL_RING0, tmp); in cik_enable_gui_idle_interrupt()
5778 WREG32(RLC_LB_CNTL, tmp); in cik_enable_lbpw()
5812 WREG32(RLC_CNTL, rlc); in cik_update_rlc()
5825 WREG32(RLC_CNTL, data); in cik_halt_rlc()
5844 WREG32(RLC_GPR_REG2, tmp); in cik_enter_rlc_safe_mode()
5865 WREG32(RLC_GPR_REG2, tmp); in cik_exit_rlc_safe_mode()
5877 WREG32(RLC_CNTL, 0); in cik_rlc_stop()
5893 WREG32(RLC_CNTL, RLC_ENABLE); in cik_rlc_start()
5920 WREG32(RLC_CGCG_CGLS_CTRL, tmp); in cik_rlc_resume()
5928 WREG32(RLC_LB_CNTR_INIT, 0); in cik_rlc_resume()
5929 WREG32(RLC_LB_CNTR_MAX, 0x00008000); in cik_rlc_resume()
5932 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); in cik_rlc_resume()
5933 WREG32(RLC_LB_PARAMS, 0x00600408); in cik_rlc_resume()
5934 WREG32(RLC_LB_CNTL, 0x80000004); in cik_rlc_resume()
5936 WREG32(RLC_MC_CNTL, 0); in cik_rlc_resume()
5937 WREG32(RLC_UCODE_CNTL, 0); in cik_rlc_resume()
5948 WREG32(RLC_GPM_UCODE_ADDR, 0); in cik_rlc_resume()
5950 WREG32(RLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_rlc_resume()
5951 WREG32(RLC_GPM_UCODE_ADDR, le32_to_cpu(hdr->header.ucode_version)); in cik_rlc_resume()
5973 WREG32(RLC_GPM_UCODE_ADDR, 0); in cik_rlc_resume()
5975 WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_rlc_resume()
5976 WREG32(RLC_GPM_UCODE_ADDR, 0); in cik_rlc_resume()
5983 WREG32(RLC_DRIVER_DMA_STATUS, 0); in cik_rlc_resume()
6002 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in cik_enable_cgcg()
6003 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in cik_enable_cgcg()
6005 WREG32(RLC_SERDES_WR_CTRL, tmp2); in cik_enable_cgcg()
6022 WREG32(RLC_CGCG_CGLS_CTRL, data); in cik_enable_cgcg()
6036 WREG32(CP_MEM_SLP_CNTL, data); in cik_enable_mgcg()
6044 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); in cik_enable_mgcg()
6049 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6050 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6052 WREG32(RLC_SERDES_WR_CTRL, data); in cik_enable_mgcg()
6069 WREG32(CGTS_SM_CTRL_REG, data); in cik_enable_mgcg()
6075 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); in cik_enable_mgcg()
6080 WREG32(RLC_MEM_SLP_CNTL, data); in cik_enable_mgcg()
6086 WREG32(CP_MEM_SLP_CNTL, data); in cik_enable_mgcg()
6092 WREG32(CGTS_SM_CTRL_REG, data); in cik_enable_mgcg()
6097 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6098 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6100 WREG32(RLC_SERDES_WR_CTRL, data); in cik_enable_mgcg()
6132 WREG32(mc_cg_registers[i], data); in cik_enable_mc_ls()
6149 WREG32(mc_cg_registers[i], data); in cik_enable_mc_mgcg()
6159 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
6160 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
6165 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
6170 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
6183 WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6188 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6193 WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6198 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6215 WREG32(UVD_CGC_CTRL, data); in cik_enable_uvd_mgcg()
6224 WREG32(UVD_CGC_CTRL, data); in cik_enable_uvd_mgcg()
6259 WREG32(HDP_HOST_PATH_CNTL, data); in cik_enable_hdp_mgcg()
6275 WREG32(HDP_MEM_POWER_LS, data); in cik_enable_hdp_ls()
6363 WREG32(RLC_PG_CNTL, data); in cik_enable_sck_slowdown_on_pu()
6377 WREG32(RLC_PG_CNTL, data); in cik_enable_sck_slowdown_on_pd()
6390 WREG32(RLC_PG_CNTL, data); in cik_enable_cp_pg()
6403 WREG32(RLC_PG_CNTL, data); in cik_enable_gds_pg()
6503 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_cgpg()
6508 WREG32(RLC_AUTO_PG_CTRL, data); in cik_enable_gfx_cgpg()
6513 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_cgpg()
6518 WREG32(RLC_AUTO_PG_CTRL, data); in cik_enable_gfx_cgpg()
6572 WREG32(RLC_PG_AO_CU_MASK, tmp); in cik_init_ao_cu_mask()
6577 WREG32(RLC_MAX_PG_CU, tmp); in cik_init_ao_cu_mask()
6591 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_static_mgpg()
6605 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_dynamic_mgpg()
6617 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); in cik_init_gfx_cgpg()
6618 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6619 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6620 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size); in cik_init_gfx_cgpg()
6622 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); in cik_init_gfx_cgpg()
6624 WREG32(RLC_GPM_SCRATCH_DATA, 0); in cik_init_gfx_cgpg()
6627 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); in cik_init_gfx_cgpg()
6629 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]); in cik_init_gfx_cgpg()
6635 WREG32(RLC_PG_CNTL, data); in cik_init_gfx_cgpg()
6637 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in cik_init_gfx_cgpg()
6638 WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8); in cik_init_gfx_cgpg()
6643 WREG32(CP_RB_WPTR_POLL_CNTL, data); in cik_init_gfx_cgpg()
6646 WREG32(RLC_PG_DELAY, data); in cik_init_gfx_cgpg()
6651 WREG32(RLC_PG_DELAY_2, data); in cik_init_gfx_cgpg()
6656 WREG32(RLC_AUTO_PG_CTRL, data); in cik_init_gfx_cgpg()
6819 WREG32(IH_CNTL, ih_cntl); in cik_enable_interrupts()
6820 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_enable_interrupts()
6838 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_disable_interrupts()
6839 WREG32(IH_CNTL, ih_cntl); in cik_disable_interrupts()
6841 WREG32(IH_RB_RPTR, 0); in cik_disable_interrupts()
6842 WREG32(IH_RB_WPTR, 0); in cik_disable_interrupts()
6861 WREG32(CP_INT_CNTL_RING0, tmp); in cik_disable_interrupt_state()
6864 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
6866 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
6868 WREG32(CP_ME1_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
6869 WREG32(CP_ME1_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state()
6870 WREG32(CP_ME1_PIPE2_INT_CNTL, 0); in cik_disable_interrupt_state()
6871 WREG32(CP_ME1_PIPE3_INT_CNTL, 0); in cik_disable_interrupt_state()
6872 WREG32(CP_ME2_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
6873 WREG32(CP_ME2_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state()
6874 WREG32(CP_ME2_PIPE2_INT_CNTL, 0); in cik_disable_interrupt_state()
6875 WREG32(CP_ME2_PIPE3_INT_CNTL, 0); in cik_disable_interrupt_state()
6877 WREG32(GRBM_INT_CNTL, 0); in cik_disable_interrupt_state()
6879 WREG32(SRBM_INT_CNTL, 0); in cik_disable_interrupt_state()
6881 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6882 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6884 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6885 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6888 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6889 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6893 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6894 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6897 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6898 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6901 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6902 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6906 WREG32(DAC_AUTODETECT_INT_CONTROL, 0); in cik_disable_interrupt_state()
6910 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6912 WREG32(DC_HPD2_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6914 WREG32(DC_HPD3_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6916 WREG32(DC_HPD4_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6918 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6920 WREG32(DC_HPD6_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6958 WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8); in cik_irq_init()
6966 WREG32(INTERRUPT_CNTL, interrupt_cntl); in cik_irq_init()
6968 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in cik_irq_init()
6979 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in cik_irq_init()
6980 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in cik_irq_init()
6982 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_irq_init()
6985 WREG32(IH_RB_RPTR, 0); in cik_irq_init()
6986 WREG32(IH_RB_WPTR, 0); in cik_irq_init()
6993 WREG32(IH_CNTL, ih_cntl); in cik_irq_init()
7217 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
7219 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl); in cik_irq_set()
7220 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1); in cik_irq_set()
7222 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); in cik_irq_set()
7223 WREG32(CP_ME1_PIPE1_INT_CNTL, cp_m1p1); in cik_irq_set()
7224 WREG32(CP_ME1_PIPE2_INT_CNTL, cp_m1p2); in cik_irq_set()
7225 WREG32(CP_ME1_PIPE3_INT_CNTL, cp_m1p3); in cik_irq_set()
7226 WREG32(CP_ME2_PIPE0_INT_CNTL, cp_m2p0); in cik_irq_set()
7227 WREG32(CP_ME2_PIPE1_INT_CNTL, cp_m2p1); in cik_irq_set()
7228 WREG32(CP_ME2_PIPE2_INT_CNTL, cp_m2p2); in cik_irq_set()
7229 WREG32(CP_ME2_PIPE3_INT_CNTL, cp_m2p3); in cik_irq_set()
7231 WREG32(GRBM_INT_CNTL, grbm_int_cntl); in cik_irq_set()
7233 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in cik_irq_set()
7234 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in cik_irq_set()
7236 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in cik_irq_set()
7237 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); in cik_irq_set()
7240 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); in cik_irq_set()
7241 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in cik_irq_set()
7245 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in cik_irq_set()
7247 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_set()
7251 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_set()
7253 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_set()
7257 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_set()
7259 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, in cik_irq_set()
7263 WREG32(DC_HPD1_INT_CONTROL, hpd1); in cik_irq_set()
7264 WREG32(DC_HPD2_INT_CONTROL, hpd2); in cik_irq_set()
7265 WREG32(DC_HPD3_INT_CONTROL, hpd3); in cik_irq_set()
7266 WREG32(DC_HPD4_INT_CONTROL, hpd4); in cik_irq_set()
7267 WREG32(DC_HPD5_INT_CONTROL, hpd5); in cik_irq_set()
7268 WREG32(DC_HPD6_INT_CONTROL, hpd6); in cik_irq_set()
7315 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, in cik_irq_ack()
7318 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_ack()
7321 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7323 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7325 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7327 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7331 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_ack()
7334 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_ack()
7337 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7339 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7341 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7343 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7348 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_ack()
7351 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, in cik_irq_ack()
7354 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7356 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7358 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7360 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7366 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_irq_ack()
7371 WREG32(DC_HPD2_INT_CONTROL, tmp); in cik_irq_ack()
7376 WREG32(DC_HPD3_INT_CONTROL, tmp); in cik_irq_ack()
7381 WREG32(DC_HPD4_INT_CONTROL, tmp); in cik_irq_ack()
7386 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_irq_ack()
7391 WREG32(DC_HPD6_INT_CONTROL, tmp); in cik_irq_ack()
7396 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_irq_ack()
7401 WREG32(DC_HPD2_INT_CONTROL, tmp); in cik_irq_ack()
7406 WREG32(DC_HPD3_INT_CONTROL, tmp); in cik_irq_ack()
7411 WREG32(DC_HPD4_INT_CONTROL, tmp); in cik_irq_ack()
7416 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_irq_ack()
7421 WREG32(DC_HPD6_INT_CONTROL, tmp); in cik_irq_ack()
7501 WREG32(IH_RB_CNTL, tmp); in cik_get_ih_wptr()
7888 WREG32(SRBM_INT_ACK, 0x1); in cik_irq_process()
8083 WREG32(IH_RB_RPTR, rptr); in cik_irq_process()
8784 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_fmt()
8834 WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset, in dce8_line_buffer_adjust()
8837 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce8_line_buffer_adjust()
9336 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_watermarks()
9337 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce8_program_watermarks()
9344 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_watermarks()
9345 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce8_program_watermarks()
9349 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask); in dce8_program_watermarks()
9400 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); in cik_get_gpu_clock_counter()