3407 	struct radeon_clock_voltage_dependency_table *allowed_mclk_table =  in ci_setup_default_dpm_tables()  local
3417 	if (allowed_mclk_table == NULL)  in ci_setup_default_dpm_tables()
3419 	if (allowed_mclk_table->count < 1)  in ci_setup_default_dpm_tables()
3454 	for (i = 0; i < allowed_mclk_table->count; i++) {  in ci_setup_default_dpm_tables()
3457 		     allowed_mclk_table->entries[i].clk)) {  in ci_setup_default_dpm_tables()
3459 				allowed_mclk_table->entries[i].clk;  in ci_setup_default_dpm_tables()
3475 	allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;  in ci_setup_default_dpm_tables()
3476 	if (allowed_mclk_table) {  in ci_setup_default_dpm_tables()
3477 		for (i = 0; i < allowed_mclk_table->count; i++) {  in ci_setup_default_dpm_tables()
3479 				allowed_mclk_table->entries[i].v;  in ci_setup_default_dpm_tables()
3482 		pi->dpm_table.vddci_table.count = allowed_mclk_table->count;  in ci_setup_default_dpm_tables()
3485 	allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;  in ci_setup_default_dpm_tables()
3486 	if (allowed_mclk_table) {  in ci_setup_default_dpm_tables()
3487 		for (i = 0; i < allowed_mclk_table->count; i++) {  in ci_setup_default_dpm_tables()
3489 				allowed_mclk_table->entries[i].v;  in ci_setup_default_dpm_tables()
3492 		pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;  in ci_setup_default_dpm_tables()