35 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);  in s6e88a0_ams452ef01_reset()
49 	mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands  in s6e88a0_ams452ef01_on()
50 	mipi_dsi_dcs_write_seq(dsi, 0xcc, 0x4c); // set Pixel Clock Divider polarity  in s6e88a0_ams452ef01_on()
53 	if (ret < 0) {  in s6e88a0_ams452ef01_on()
60 	mipi_dsi_dcs_write_seq(dsi, 0xca,  in s6e88a0_ams452ef01_on()
61 			       0x01, 0x00, 0x01, 0x00, 0x01, 0x00,	// V255 RR,GG,BB  in s6e88a0_ams452ef01_on()
62 			       0x80, 0x80, 0x80,			// V203 R,G,B  in s6e88a0_ams452ef01_on()
63 			       0x80, 0x80, 0x80,			// V151 R,G,B  in s6e88a0_ams452ef01_on()
64 			       0x80, 0x80, 0x80,			// V87  R,G,B  in s6e88a0_ams452ef01_on()
65 			       0x80, 0x80, 0x80,			// V51  R,G,B  in s6e88a0_ams452ef01_on()
66 			       0x80, 0x80, 0x80,			// V35  R,G,B  in s6e88a0_ams452ef01_on()
67 			       0x80, 0x80, 0x80,			// V23  R,G,B  in s6e88a0_ams452ef01_on()
68 			       0x80, 0x80, 0x80,			// V11  R,G,B  in s6e88a0_ams452ef01_on()
69 			       0x6b, 0x68, 0x71,			// V3   R,G,B  in s6e88a0_ams452ef01_on()
70 			       0x00, 0x00, 0x00);			// V1   R,G,B  in s6e88a0_ams452ef01_on()
72 	mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a);  in s6e88a0_ams452ef01_on()
73 	mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x2c, 0x0b); // set default elvss voltage  in s6e88a0_ams452ef01_on()
74 	mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00);  in s6e88a0_ams452ef01_on()
75 	mipi_dsi_dcs_write_seq(dsi, 0xf7, 0x03); // gamma/aor update  in s6e88a0_ams452ef01_on()
76 	mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands  in s6e88a0_ams452ef01_on()
79 	if (ret < 0) {  in s6e88a0_ams452ef01_on()
84 	return 0;  in s6e88a0_ams452ef01_on()
96 	if (ret < 0) {  in s6e88a0_ams452ef01_off()
103 	if (ret < 0) {  in s6e88a0_ams452ef01_off()
109 	return 0;  in s6e88a0_ams452ef01_off()
119 		return 0;  in s6e88a0_ams452ef01_prepare()
122 	if (ret < 0) {  in s6e88a0_ams452ef01_prepare()
130 	if (ret < 0) {  in s6e88a0_ams452ef01_prepare()
132 		gpiod_set_value_cansleep(ctx->reset_gpio, 0);  in s6e88a0_ams452ef01_prepare()
139 	return 0;  in s6e88a0_ams452ef01_prepare()
149 		return 0;  in s6e88a0_ams452ef01_unprepare()
152 	if (ret < 0)  in s6e88a0_ams452ef01_unprepare()
155 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);  in s6e88a0_ams452ef01_unprepare()
159 	return 0;  in s6e88a0_ams452ef01_unprepare()
211 	ctx->supplies[0].supply = "vdd3";  in s6e88a0_ams452ef01_probe()
215 	if (ret < 0) {  in s6e88a0_ams452ef01_probe()
240 	if (ret < 0) {  in s6e88a0_ams452ef01_probe()
246 	return 0;  in s6e88a0_ams452ef01_probe()
255 	if (ret < 0)  in s6e88a0_ams452ef01_remove()