Lines Matching refs:ram
70 nvkm_sddr3_calc(struct nvkm_ram *ram) in nvkm_sddr3_calc() argument
74 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr3_calc()
76 switch (ram->next->bios.timing_ver) { in nvkm_sddr3_calc()
78 if (ram->next->bios.timing_hdr < 0x17) { in nvkm_sddr3_calc()
82 CWL = ram->next->bios.timing_10_CWL; in nvkm_sddr3_calc()
83 CL = ram->next->bios.timing_10_CL; in nvkm_sddr3_calc()
84 WR = ram->next->bios.timing_10_WR; in nvkm_sddr3_calc()
85 ODT = ram->next->bios.timing_10_ODT; in nvkm_sddr3_calc()
88 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; in nvkm_sddr3_calc()
89 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; in nvkm_sddr3_calc()
90 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_sddr3_calc()
92 ODT = (ram->mr[1] & 0x004) >> 2 | in nvkm_sddr3_calc()
93 (ram->mr[1] & 0x040) >> 5 | in nvkm_sddr3_calc()
94 (ram->mr[1] & 0x200) >> 7; in nvkm_sddr3_calc()
106 ram->mr[0] &= ~0xf74; in nvkm_sddr3_calc()
107 ram->mr[0] |= (WR & 0x07) << 9; in nvkm_sddr3_calc()
108 ram->mr[0] |= (CL & 0x0e) << 3; in nvkm_sddr3_calc()
109 ram->mr[0] |= (CL & 0x01) << 2; in nvkm_sddr3_calc()
111 ram->mr[1] &= ~0x245; in nvkm_sddr3_calc()
112 ram->mr[1] |= (ODT & 0x1) << 2; in nvkm_sddr3_calc()
113 ram->mr[1] |= (ODT & 0x2) << 5; in nvkm_sddr3_calc()
114 ram->mr[1] |= (ODT & 0x4) << 7; in nvkm_sddr3_calc()
115 ram->mr[1] |= !DLL; in nvkm_sddr3_calc()
117 ram->mr[2] &= ~0x038; in nvkm_sddr3_calc()
118 ram->mr[2] |= (CWL & 0x07) << 3; in nvkm_sddr3_calc()