346 #define T(t) cfg->timing_10_##t  macro
362 	switch ((!T(CWL)) * ram->base.type) {  in gt215_ram_timing_calc()
364 		T(CWL) = T(CL) - 1;  in gt215_ram_timing_calc()
367 		T(CWL) = ((cur2 & 0xff000000) >> 24) + 1;  in gt215_ram_timing_calc()
374 	timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC));  in gt215_ram_timing_calc()
375 	timing[1] = (T(WR) + 1 + T(CWL)) << 24 |  in gt215_ram_timing_calc()
376 		    max_t(u8,T(18), 1) << 16 |  in gt215_ram_timing_calc()
377 		    (T(WTR) + 1 + T(CWL)) << 8 |  in gt215_ram_timing_calc()
378 		    (5 + T(CL) - T(CWL));  in gt215_ram_timing_calc()
379 	timing[2] = (T(CWL) - 1) << 24 |  in gt215_ram_timing_calc()
380 		    (T(RRD) << 16) |  in gt215_ram_timing_calc()
381 		    (T(RCDWR) << 8) |  in gt215_ram_timing_calc()
382 		    T(RCDRD);  in gt215_ram_timing_calc()
384 		    (0x30 + T(CL)) << 24 |  in gt215_ram_timing_calc()
385 		    (0xb + T(CL)) << 8 |  in gt215_ram_timing_calc()
386 		    (T(CL) - 1);  in gt215_ram_timing_calc()
387 	timing[4] = T(20) << 24 |  in gt215_ram_timing_calc()
388 		    T(21) << 16 |  in gt215_ram_timing_calc()
389 		    T(13) << 8 |  in gt215_ram_timing_calc()
390 		    T(13);  in gt215_ram_timing_calc()
391 	timing[5] = T(RFC) << 24 |  in gt215_ram_timing_calc()
392 		    max_t(u8,T(RCDRD), T(RCDWR)) << 16 |  in gt215_ram_timing_calc()
393 		    max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 |  in gt215_ram_timing_calc()
394 		    T(RP);  in gt215_ram_timing_calc()
395 	timing[6] = (0x5a + T(CL)) << 16 |  in gt215_ram_timing_calc()
396 		    max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 |  in gt215_ram_timing_calc()
397 		    (0x50 + T(CL) - T(CWL));  in gt215_ram_timing_calc()
399 		    ((tUNK_base + T(CL)) << 16) |  in gt215_ram_timing_calc()
408 			timing[8] |= T(CL);  in gt215_ram_timing_calc()
421 #undef T