67 	struct nvkm_device *device = clk->base.subdev.device;  in gk20a_pllg_read_mnp()  local
70 	val = nvkm_rd32(device, GPCPLL_COEFF);  in gk20a_pllg_read_mnp()
79 	struct nvkm_device *device = clk->base.subdev.device;  in gk20a_pllg_write_mnp()  local
85 	nvkm_wr32(device, GPCPLL_COEFF, val);  in gk20a_pllg_write_mnp()
214 	struct nvkm_device *device = subdev->device;  in gk20a_pllg_slide()  local
225 	nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,  in gk20a_pllg_slide()
236 	nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,  in gk20a_pllg_slide()
241 	if (nvkm_wait_usec(device, 500, GPC_BCAST_NDIV_SLOWDOWN_DEBUG,  in gk20a_pllg_slide()
247 	nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,  in gk20a_pllg_slide()
250 	nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN);  in gk20a_pllg_slide()
258 	struct nvkm_device *device = clk->base.subdev.device;  in gk20a_pllg_enable()  local
261 	nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);  in gk20a_pllg_enable()
262 	nvkm_rd32(device, GPCPLL_CFG);  in gk20a_pllg_enable()
265 	val = nvkm_rd32(device, GPCPLL_CFG);  in gk20a_pllg_enable()
268 		nvkm_wr32(device, GPCPLL_CFG, val);  in gk20a_pllg_enable()
272 	if (nvkm_wait_usec(device, 300, GPCPLL_CFG, GPCPLL_CFG_LOCK,  in gk20a_pllg_enable()
277 	nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT),  in gk20a_pllg_enable()
286 	struct nvkm_device *device = clk->base.subdev.device;  in gk20a_pllg_disable()  local
289 	nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0);  in gk20a_pllg_disable()
291 	nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);  in gk20a_pllg_disable()
292 	nvkm_rd32(device, GPCPLL_CFG);  in gk20a_pllg_disable()
299 	struct nvkm_device *device = subdev->device;  in gk20a_pllg_program_mnp()  local
306 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,  in gk20a_pllg_program_mnp()
309 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,  in gk20a_pllg_program_mnp()
311 	nvkm_rd32(device, GPC2CLK_OUT);  in gk20a_pllg_program_mnp()
324 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,  in gk20a_pllg_program_mnp()
327 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,  in gk20a_pllg_program_mnp()
329 	nvkm_rd32(device, GPC2CLK_OUT);  in gk20a_pllg_program_mnp()
464 	struct nvkm_device *device = subdev->device;  in gk20a_clk_read()  local
469 		return device->crystal;  in gk20a_clk_read()
510 	struct nvkm_device *device = subdev->device;  in gk20a_clk_setup_slide()  local
534 	nvkm_mask(device, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT,  in gk20a_clk_setup_slide()
536 	nvkm_mask(device, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT,  in gk20a_clk_setup_slide()
545 	struct nvkm_device *device = base->subdev.device;  in gk20a_clk_fini()  local
561 	nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_IDDQ, 1);  in gk20a_clk_fini()
569 	struct nvkm_device *device = subdev->device;  in gk20a_clk_init()  local
573 	nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_IDDQ, 0);  in gk20a_clk_init()
574 	nvkm_rd32(device, GPCPLL_CFG);  in gk20a_clk_init()
577 	nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK,  in gk20a_clk_init()
613 gk20a_clk_ctor(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,  in gk20a_clk_ctor()  argument
617 	struct nvkm_device_tegra *tdev = device->func->tegra(device);  in gk20a_clk_ctor()
630 	ret = nvkm_clk_ctor(func, device, type, inst, true, &clk->base);  in gk20a_clk_ctor()
641 gk20a_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,  in gk20a_clk_new()  argument
652 	ret = gk20a_clk_ctor(device, type, inst, &gk20a_clk, &gk20a_pllg_params, clk);  in gk20a_clk_new()