42 		u8 pstate, u8 domain, u32 input)  in nvkm_clk_adjust()  argument
49 	data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE);  in nvkm_clk_adjust()
112 nvkm_cstate_find_best(struct nvkm_clk *clk, struct nvkm_pstate *pstate,  in nvkm_cstate_find_best()  argument
119 	if (!pstate || !cstate)  in nvkm_cstate_find_best()
136 	list_for_each_entry_from_reverse(cstate, &pstate->list, head) {  in nvkm_cstate_find_best()
145 nvkm_cstate_get(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)  in nvkm_cstate_get()  argument
149 		return list_last_entry(&pstate->list, typeof(*cstate), head);  in nvkm_cstate_get()
151 		list_for_each_entry(cstate, &pstate->list, head) {  in nvkm_cstate_get()
160 nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)  in nvkm_cstate_prog()  argument
169 	if (!list_empty(&pstate->list)) {  in nvkm_cstate_prog()
170 		cstate = nvkm_cstate_get(clk, pstate, cstatei);  in nvkm_cstate_prog()
171 		cstate = nvkm_cstate_find_best(clk, pstate, cstate);  in nvkm_cstate_prog()
175 		cstate = &pstate->base;  in nvkm_cstate_prog()
179 		ret = nvkm_therm_cstate(therm, pstate->fanspeed, +1);  in nvkm_cstate_prog()
188 				       pstate->base.voltage, clk->temp, +1);  in nvkm_cstate_prog()
203 				       pstate->base.voltage, clk->temp, -1);  in nvkm_cstate_prog()
209 		ret = nvkm_therm_cstate(therm, pstate->fanspeed, -1);  in nvkm_cstate_prog()
225 nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate)  in nvkm_cstate_new()  argument
246 	*cstate = pstate->base;  in nvkm_cstate_new()
252 			u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate,  in nvkm_cstate_new()
259 	list_add(&cstate->head, &pstate->list);  in nvkm_cstate_new()
272 	struct nvkm_pstate *pstate;  in nvkm_pstate_prog()  local
275 	list_for_each_entry(pstate, &clk->states, head) {  in nvkm_pstate_prog()
281 	clk->pstate = pstatei;  in nvkm_pstate_prog()
283 	nvkm_pcie_set_link(pci, pstate->pcie_speed, pstate->pcie_width);  in nvkm_pstate_prog()
287 		int khz = pstate->base.domain[nv_clk_src_mem];  in nvkm_pstate_prog()
296 	return nvkm_cstate_prog(clk, pstate, NVKM_CLK_CSTATE_HIGHEST);  in nvkm_pstate_prog()
304 	int pstate;  in nvkm_pstate_work()  local
311 		   clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc,  in nvkm_pstate_work()
314 	pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc;  in nvkm_pstate_work()
315 	if (clk->state_nr && pstate != -1) {  in nvkm_pstate_work()
316 		pstate = (pstate < 0) ? clk->astate : pstate;  in nvkm_pstate_work()
317 		pstate = min(pstate, clk->state_nr - 1);  in nvkm_pstate_work()
318 		pstate = max(pstate, clk->dstate);  in nvkm_pstate_work()
320 		pstate = clk->pstate = -1;  in nvkm_pstate_work()
323 	nvkm_trace(subdev, "-> %d\n", pstate);  in nvkm_pstate_work()
324 	if (pstate != clk->pstate) {  in nvkm_pstate_work()
325 		int ret = nvkm_pstate_prog(clk, pstate);  in nvkm_pstate_work()
328 				   pstate, ret);  in nvkm_pstate_work()
346 nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate)  in nvkm_pstate_info()  argument
355 	if (pstate->pstate != 0xff)  in nvkm_pstate_info()
356 		snprintf(name, sizeof(name), "%02x", pstate->pstate);  in nvkm_pstate_info()
359 		u32 lo = pstate->base.domain[clock->name];  in nvkm_pstate_info()
365 		list_for_each_entry(cstate, &pstate->list, head) {  in nvkm_pstate_info()
389 nvkm_pstate_del(struct nvkm_pstate *pstate)  in nvkm_pstate_del()  argument
393 	list_for_each_entry_safe(cstate, temp, &pstate->list, head) {  in nvkm_pstate_del()
397 	list_del(&pstate->head);  in nvkm_pstate_del()
398 	kfree(pstate);  in nvkm_pstate_del()
406 	struct nvkm_pstate *pstate;  in nvkm_pstate_new()  local
416 	if (perfE.pstate == 0xff)  in nvkm_pstate_new()
419 	pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);  in nvkm_pstate_new()
420 	if (!pstate)  in nvkm_pstate_new()
423 	INIT_LIST_HEAD(&pstate->list);  in nvkm_pstate_new()
425 	pstate->pstate = perfE.pstate;  in nvkm_pstate_new()
426 	pstate->fanspeed = perfE.fanspeed;  in nvkm_pstate_new()
427 	pstate->pcie_speed = perfE.pcie_speed;  in nvkm_pstate_new()
428 	pstate->pcie_width = perfE.pcie_width;  in nvkm_pstate_new()
429 	cstate = &pstate->base;  in nvkm_pstate_new()
447 							 pstate->pstate,  in nvkm_pstate_new()
455 	data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE);  in nvkm_pstate_new()
459 			nvkm_cstate_new(clk, idx, pstate);  in nvkm_pstate_new()
463 	nvkm_pstate_info(clk, pstate);  in nvkm_pstate_new()
464 	list_add_tail(&pstate->head, &clk->states);  in nvkm_pstate_new()
475 	struct nvkm_pstate *pstate;  in nvkm_clk_ustate_update()  local
482 		list_for_each_entry(pstate, &clk->states, head) {  in nvkm_clk_ustate_update()
483 			if (pstate->pstate == req)  in nvkm_clk_ustate_update()
488 		if (pstate->pstate != req)  in nvkm_clk_ustate_update()
598 	clk->bstate.pstate = 0xff;  in nvkm_clk_init()
617 	clk->pstate = -1;  in nvkm_clk_init()
627 	struct nvkm_pstate *pstate, *temp;  in nvkm_clk_dtor()  local
633 	list_for_each_entry_safe(pstate, temp, &clk->states, head) {  in nvkm_clk_dtor()
634 		nvkm_pstate_del(pstate);  in nvkm_clk_dtor()