Lines Matching refs:subdev
26 loader_config_dump(struct nvkm_subdev *subdev, const struct loader_config *hdr) in loader_config_dump() argument
28 nvkm_debug(subdev, "loaderConfig\n"); in loader_config_dump()
29 nvkm_debug(subdev, "\tdmaIdx : %d\n", hdr->dma_idx); in loader_config_dump()
30 nvkm_debug(subdev, "\tcodeDmaBase : 0x%xx\n", hdr->code_dma_base); in loader_config_dump()
31 nvkm_debug(subdev, "\tcodeSizeTotal : 0x%x\n", hdr->code_size_total); in loader_config_dump()
32 nvkm_debug(subdev, "\tcodeSizeToLoad: 0x%x\n", hdr->code_size_to_load); in loader_config_dump()
33 nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point); in loader_config_dump()
34 nvkm_debug(subdev, "\tdataDmaBase : 0x%x\n", hdr->data_dma_base); in loader_config_dump()
35 nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size); in loader_config_dump()
36 nvkm_debug(subdev, "\toverlayDmaBase: 0x%x\n", hdr->overlay_dma_base); in loader_config_dump()
37 nvkm_debug(subdev, "\targc : 0x%08x\n", hdr->argc); in loader_config_dump()
38 nvkm_debug(subdev, "\targv : 0x%08x\n", hdr->argv); in loader_config_dump()
39 nvkm_debug(subdev, "\tcodeDmaBase1 : 0x%x\n", hdr->code_dma_base1); in loader_config_dump()
40 nvkm_debug(subdev, "\tdataDmaBase1 : 0x%x\n", hdr->data_dma_base1); in loader_config_dump()
41 nvkm_debug(subdev, "\tovlyDmaBase1 : 0x%x\n", hdr->overlay_dma_base1); in loader_config_dump()
45 loader_config_v1_dump(struct nvkm_subdev *subdev, in loader_config_v1_dump() argument
48 nvkm_debug(subdev, "loaderConfig\n"); in loader_config_v1_dump()
49 nvkm_debug(subdev, "\treserved : 0x%08x\n", hdr->reserved); in loader_config_v1_dump()
50 nvkm_debug(subdev, "\tdmaIdx : %d\n", hdr->dma_idx); in loader_config_v1_dump()
51 nvkm_debug(subdev, "\tcodeDmaBase : 0x%llxx\n", hdr->code_dma_base); in loader_config_v1_dump()
52 nvkm_debug(subdev, "\tcodeSizeTotal : 0x%x\n", hdr->code_size_total); in loader_config_v1_dump()
53 nvkm_debug(subdev, "\tcodeSizeToLoad: 0x%x\n", hdr->code_size_to_load); in loader_config_v1_dump()
54 nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point); in loader_config_v1_dump()
55 nvkm_debug(subdev, "\tdataDmaBase : 0x%llx\n", hdr->data_dma_base); in loader_config_v1_dump()
56 nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size); in loader_config_v1_dump()
57 nvkm_debug(subdev, "\toverlayDmaBase: 0x%llx\n", hdr->overlay_dma_base); in loader_config_v1_dump()
58 nvkm_debug(subdev, "\targc : 0x%08x\n", hdr->argc); in loader_config_v1_dump()
59 nvkm_debug(subdev, "\targv : 0x%08x\n", hdr->argv); in loader_config_v1_dump()
63 flcn_bl_dmem_desc_dump(struct nvkm_subdev *subdev, in flcn_bl_dmem_desc_dump() argument
66 nvkm_debug(subdev, "flcnBlDmemDesc\n"); in flcn_bl_dmem_desc_dump()
67 nvkm_debug(subdev, "\treserved : 0x%08x 0x%08x 0x%08x 0x%08x\n", in flcn_bl_dmem_desc_dump()
70 nvkm_debug(subdev, "\tsignature : 0x%08x 0x%08x 0x%08x 0x%08x\n", in flcn_bl_dmem_desc_dump()
73 nvkm_debug(subdev, "\tctxDma : %d\n", hdr->ctx_dma); in flcn_bl_dmem_desc_dump()
74 nvkm_debug(subdev, "\tcodeDmaBase : 0x%x\n", hdr->code_dma_base); in flcn_bl_dmem_desc_dump()
75 nvkm_debug(subdev, "\tnonSecCodeOff : 0x%x\n", hdr->non_sec_code_off); in flcn_bl_dmem_desc_dump()
76 nvkm_debug(subdev, "\tnonSecCodeSize: 0x%x\n", hdr->non_sec_code_size); in flcn_bl_dmem_desc_dump()
77 nvkm_debug(subdev, "\tsecCodeOff : 0x%x\n", hdr->sec_code_off); in flcn_bl_dmem_desc_dump()
78 nvkm_debug(subdev, "\tsecCodeSize : 0x%x\n", hdr->sec_code_size); in flcn_bl_dmem_desc_dump()
79 nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point); in flcn_bl_dmem_desc_dump()
80 nvkm_debug(subdev, "\tdataDmaBase : 0x%x\n", hdr->data_dma_base); in flcn_bl_dmem_desc_dump()
81 nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size); in flcn_bl_dmem_desc_dump()
82 nvkm_debug(subdev, "\tcodeDmaBase1 : 0x%x\n", hdr->code_dma_base1); in flcn_bl_dmem_desc_dump()
83 nvkm_debug(subdev, "\tdataDmaBase1 : 0x%x\n", hdr->data_dma_base1); in flcn_bl_dmem_desc_dump()
87 flcn_bl_dmem_desc_v1_dump(struct nvkm_subdev *subdev, in flcn_bl_dmem_desc_v1_dump() argument
90 nvkm_debug(subdev, "flcnBlDmemDesc\n"); in flcn_bl_dmem_desc_v1_dump()
91 nvkm_debug(subdev, "\treserved : 0x%08x 0x%08x 0x%08x 0x%08x\n", in flcn_bl_dmem_desc_v1_dump()
94 nvkm_debug(subdev, "\tsignature : 0x%08x 0x%08x 0x%08x 0x%08x\n", in flcn_bl_dmem_desc_v1_dump()
97 nvkm_debug(subdev, "\tctxDma : %d\n", hdr->ctx_dma); in flcn_bl_dmem_desc_v1_dump()
98 nvkm_debug(subdev, "\tcodeDmaBase : 0x%llx\n", hdr->code_dma_base); in flcn_bl_dmem_desc_v1_dump()
99 nvkm_debug(subdev, "\tnonSecCodeOff : 0x%x\n", hdr->non_sec_code_off); in flcn_bl_dmem_desc_v1_dump()
100 nvkm_debug(subdev, "\tnonSecCodeSize: 0x%x\n", hdr->non_sec_code_size); in flcn_bl_dmem_desc_v1_dump()
101 nvkm_debug(subdev, "\tsecCodeOff : 0x%x\n", hdr->sec_code_off); in flcn_bl_dmem_desc_v1_dump()
102 nvkm_debug(subdev, "\tsecCodeSize : 0x%x\n", hdr->sec_code_size); in flcn_bl_dmem_desc_v1_dump()
103 nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point); in flcn_bl_dmem_desc_v1_dump()
104 nvkm_debug(subdev, "\tdataDmaBase : 0x%llx\n", hdr->data_dma_base); in flcn_bl_dmem_desc_v1_dump()
105 nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size); in flcn_bl_dmem_desc_v1_dump()
109 flcn_bl_dmem_desc_v2_dump(struct nvkm_subdev *subdev, in flcn_bl_dmem_desc_v2_dump() argument
112 flcn_bl_dmem_desc_v1_dump(subdev, (void *)hdr); in flcn_bl_dmem_desc_v2_dump()
113 nvkm_debug(subdev, "\targc : 0x%08x\n", hdr->argc); in flcn_bl_dmem_desc_v2_dump()
114 nvkm_debug(subdev, "\targv : 0x%08x\n", hdr->argv); in flcn_bl_dmem_desc_v2_dump()