Lines Matching refs:device
51 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_zbc_clear_color() local
53 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); in gf100_gr_zbc_clear_color()
54 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); in gf100_gr_zbc_clear_color()
55 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); in gf100_gr_zbc_clear_color()
56 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); in gf100_gr_zbc_clear_color()
58 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); in gf100_gr_zbc_clear_color()
59 nvkm_wr32(device, 0x405820, zbc); in gf100_gr_zbc_clear_color()
60 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ in gf100_gr_zbc_clear_color()
67 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; in gf100_gr_zbc_color_get()
102 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_zbc_clear_depth() local
104 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); in gf100_gr_zbc_clear_depth()
105 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); in gf100_gr_zbc_clear_depth()
106 nvkm_wr32(device, 0x405820, zbc); in gf100_gr_zbc_clear_depth()
107 nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ in gf100_gr_zbc_clear_depth()
114 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; in gf100_gr_zbc_depth_get()
251 gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data) in gf100_gr_mthd_set_shader_exceptions() argument
253 nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000); in gf100_gr_mthd_set_shader_exceptions()
254 nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000); in gf100_gr_mthd_set_shader_exceptions()
258 gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data) in gf100_gr_mthd_sw() argument
265 gf100_gr_mthd_set_shader_exceptions(device, data); in gf100_gr_mthd_sw()
327 ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, in gf100_gr_chan_bind()
384 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_chan_new() local
417 if (device->card_type < GP100) { in gf100_gr_chan_new()
455 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100, in gf100_gr_chan_new()
746 return nvkm_rd32(gr->engine.subdev.device, 0x409b00); in gf100_gr_ctxsw_inst()
752 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_ctrl_ctxsw() local
754 nvkm_wr32(device, 0x409804, 0xffffffff); in gf100_gr_fecs_ctrl_ctxsw()
755 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_ctrl_ctxsw()
756 nvkm_wr32(device, 0x409500, 0xffffffff); in gf100_gr_fecs_ctrl_ctxsw()
757 nvkm_wr32(device, 0x409504, mthd); in gf100_gr_fecs_ctrl_ctxsw()
758 nvkm_msec(device, 2000, in gf100_gr_fecs_ctrl_ctxsw()
759 u32 stat = nvkm_rd32(device, 0x409804); in gf100_gr_fecs_ctrl_ctxsw()
816 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_wfi_golden_save() local
818 nvkm_mask(device, 0x409800, 0x00000003, 0x00000000); in gf100_gr_fecs_wfi_golden_save()
819 nvkm_wr32(device, 0x409500, inst); in gf100_gr_fecs_wfi_golden_save()
820 nvkm_wr32(device, 0x409504, 0x00000009); in gf100_gr_fecs_wfi_golden_save()
821 nvkm_msec(device, 2000, in gf100_gr_fecs_wfi_golden_save()
822 u32 stat = nvkm_rd32(device, 0x409800); in gf100_gr_fecs_wfi_golden_save()
835 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_bind_pointer() local
837 nvkm_mask(device, 0x409800, 0x00000030, 0x00000000); in gf100_gr_fecs_bind_pointer()
838 nvkm_wr32(device, 0x409500, inst); in gf100_gr_fecs_bind_pointer()
839 nvkm_wr32(device, 0x409504, 0x00000003); in gf100_gr_fecs_bind_pointer()
840 nvkm_msec(device, 2000, in gf100_gr_fecs_bind_pointer()
841 u32 stat = nvkm_rd32(device, 0x409800); in gf100_gr_fecs_bind_pointer()
854 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_set_reglist_virtual_address() local
856 nvkm_wr32(device, 0x409810, addr >> 8); in gf100_gr_fecs_set_reglist_virtual_address()
857 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_set_reglist_virtual_address()
858 nvkm_wr32(device, 0x409500, 0x00000001); in gf100_gr_fecs_set_reglist_virtual_address()
859 nvkm_wr32(device, 0x409504, 0x00000032); in gf100_gr_fecs_set_reglist_virtual_address()
860 nvkm_msec(device, 2000, in gf100_gr_fecs_set_reglist_virtual_address()
861 if (nvkm_rd32(device, 0x409800) == 0x00000001) in gf100_gr_fecs_set_reglist_virtual_address()
871 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_set_reglist_bind_instance() local
873 nvkm_wr32(device, 0x409810, inst); in gf100_gr_fecs_set_reglist_bind_instance()
874 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_set_reglist_bind_instance()
875 nvkm_wr32(device, 0x409500, 0x00000001); in gf100_gr_fecs_set_reglist_bind_instance()
876 nvkm_wr32(device, 0x409504, 0x00000031); in gf100_gr_fecs_set_reglist_bind_instance()
877 nvkm_msec(device, 2000, in gf100_gr_fecs_set_reglist_bind_instance()
878 if (nvkm_rd32(device, 0x409800) == 0x00000001) in gf100_gr_fecs_set_reglist_bind_instance()
888 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_discover_reglist_image_size() local
890 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_discover_reglist_image_size()
891 nvkm_wr32(device, 0x409500, 0x00000001); in gf100_gr_fecs_discover_reglist_image_size()
892 nvkm_wr32(device, 0x409504, 0x00000030); in gf100_gr_fecs_discover_reglist_image_size()
893 nvkm_msec(device, 2000, in gf100_gr_fecs_discover_reglist_image_size()
894 if ((*psize = nvkm_rd32(device, 0x409800))) in gf100_gr_fecs_discover_reglist_image_size()
926 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_discover_pm_image_size() local
928 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_discover_pm_image_size()
929 nvkm_wr32(device, 0x409500, 0x00000000); in gf100_gr_fecs_discover_pm_image_size()
930 nvkm_wr32(device, 0x409504, 0x00000025); in gf100_gr_fecs_discover_pm_image_size()
931 nvkm_msec(device, 2000, in gf100_gr_fecs_discover_pm_image_size()
932 if ((*psize = nvkm_rd32(device, 0x409800))) in gf100_gr_fecs_discover_pm_image_size()
942 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_discover_zcull_image_size() local
944 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_discover_zcull_image_size()
945 nvkm_wr32(device, 0x409500, 0x00000000); in gf100_gr_fecs_discover_zcull_image_size()
946 nvkm_wr32(device, 0x409504, 0x00000016); in gf100_gr_fecs_discover_zcull_image_size()
947 nvkm_msec(device, 2000, in gf100_gr_fecs_discover_zcull_image_size()
948 if ((*psize = nvkm_rd32(device, 0x409800))) in gf100_gr_fecs_discover_zcull_image_size()
958 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_discover_image_size() local
960 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_discover_image_size()
961 nvkm_wr32(device, 0x409500, 0x00000000); in gf100_gr_fecs_discover_image_size()
962 nvkm_wr32(device, 0x409504, 0x00000010); in gf100_gr_fecs_discover_image_size()
963 nvkm_msec(device, 2000, in gf100_gr_fecs_discover_image_size()
964 if ((*psize = nvkm_rd32(device, 0x409800))) in gf100_gr_fecs_discover_image_size()
974 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_set_watchdog_timeout() local
976 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_fecs_set_watchdog_timeout()
977 nvkm_wr32(device, 0x409500, timeout); in gf100_gr_fecs_set_watchdog_timeout()
978 nvkm_wr32(device, 0x409504, 0x00000021); in gf100_gr_fecs_set_watchdog_timeout()
986 u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c); in gf100_gr_chsw_load()
990 u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808); in gf100_gr_chsw_load()
1000 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_rops() local
1001 return (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; in gf100_gr_rops()
1015 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; in gf100_gr_zbc_init()
1052 struct nvkm_device *device = subdev->device; in gf100_gr_wait_idle() local
1061 nvkm_rd32(device, 0x400700); in gf100_gr_wait_idle()
1063 gr_enabled = nvkm_rd32(device, 0x200) & 0x1000; in gf100_gr_wait_idle()
1065 gr_busy = nvkm_rd32(device, 0x40060c) & 0x1; in gf100_gr_wait_idle()
1080 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_mmio() local
1088 nvkm_wr32(device, addr, init->data); in gf100_gr_mmio()
1097 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_icmd() local
1102 nvkm_wr32(device, 0x400208, 0x80000000); in gf100_gr_icmd()
1109 nvkm_wr32(device, 0x400204, init->data); in gf100_gr_icmd()
1111 nvkm_wr32(device, 0x40020c, upper_32_bits(init->data)); in gf100_gr_icmd()
1116 nvkm_wr32(device, 0x400200, addr); in gf100_gr_icmd()
1123 nvkm_msec(device, 2000, in gf100_gr_icmd()
1124 if (!(nvkm_rd32(device, 0x400700) & 0x00000004)) in gf100_gr_icmd()
1131 nvkm_wr32(device, 0x400208, 0x00000000); in gf100_gr_icmd()
1137 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_mthd() local
1148 nvkm_wr32(device, 0x40448c, init->data); in gf100_gr_mthd()
1153 nvkm_wr32(device, 0x404488, ctrl | (addr << 14)); in gf100_gr_mthd()
1237 struct nvkm_device *device = subdev->device; in gf100_gr_trap_gpc_rop() local
1241 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; in gf100_gr_trap_gpc_rop()
1242 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); in gf100_gr_trap_gpc_rop()
1243 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); in gf100_gr_trap_gpc_rop()
1244 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); in gf100_gr_trap_gpc_rop()
1252 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); in gf100_gr_trap_gpc_rop()
1298 struct nvkm_device *device = subdev->device; in gf100_gr_trap_mp() local
1299 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); in gf100_gr_trap_mp()
1300 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); in gf100_gr_trap_mp()
1311 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); in gf100_gr_trap_mp()
1312 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); in gf100_gr_trap_mp()
1319 struct nvkm_device *device = subdev->device; in gf100_gr_trap_tpc() local
1320 u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); in gf100_gr_trap_tpc()
1323 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); in gf100_gr_trap_tpc()
1325 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); in gf100_gr_trap_tpc()
1335 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); in gf100_gr_trap_tpc()
1337 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); in gf100_gr_trap_tpc()
1342 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); in gf100_gr_trap_tpc()
1344 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); in gf100_gr_trap_tpc()
1349 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0430)); in gf100_gr_trap_tpc()
1351 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0430), 0xc0000000); in gf100_gr_trap_tpc()
1364 struct nvkm_device *device = subdev->device; in gf100_gr_trap_gpc() local
1365 u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); in gf100_gr_trap_gpc()
1374 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); in gf100_gr_trap_gpc()
1376 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); in gf100_gr_trap_gpc()
1381 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); in gf100_gr_trap_gpc()
1383 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); in gf100_gr_trap_gpc()
1388 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); in gf100_gr_trap_gpc()
1390 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); in gf100_gr_trap_gpc()
1398 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); in gf100_gr_trap_gpc()
1412 struct nvkm_device *device = subdev->device; in gf100_gr_trap_intr() local
1414 u32 trap = nvkm_rd32(device, 0x400108); in gf100_gr_trap_intr()
1418 u32 stat = nvkm_rd32(device, 0x404000); in gf100_gr_trap_intr()
1423 nvkm_wr32(device, 0x404000, 0xc0000000); in gf100_gr_trap_intr()
1424 nvkm_wr32(device, 0x400108, 0x00000001); in gf100_gr_trap_intr()
1429 u32 stat = nvkm_rd32(device, 0x404600); in gf100_gr_trap_intr()
1435 nvkm_wr32(device, 0x404600, 0xc0000000); in gf100_gr_trap_intr()
1436 nvkm_wr32(device, 0x400108, 0x00000002); in gf100_gr_trap_intr()
1441 u32 stat = nvkm_rd32(device, 0x408030); in gf100_gr_trap_intr()
1446 nvkm_wr32(device, 0x408030, 0xc0000000); in gf100_gr_trap_intr()
1447 nvkm_wr32(device, 0x400108, 0x00000008); in gf100_gr_trap_intr()
1452 u32 stat = nvkm_rd32(device, 0x405840); in gf100_gr_trap_intr()
1455 nvkm_wr32(device, 0x405840, 0xc0000000); in gf100_gr_trap_intr()
1456 nvkm_wr32(device, 0x400108, 0x00000010); in gf100_gr_trap_intr()
1461 u32 stat = nvkm_rd32(device, 0x40601c); in gf100_gr_trap_intr()
1467 nvkm_wr32(device, 0x40601c, 0xc0000000); in gf100_gr_trap_intr()
1468 nvkm_wr32(device, 0x400108, 0x00000040); in gf100_gr_trap_intr()
1473 u32 stat = nvkm_rd32(device, 0x404490); in gf100_gr_trap_intr()
1474 u32 pc = nvkm_rd32(device, 0x404494); in gf100_gr_trap_intr()
1475 u32 op = nvkm_rd32(device, 0x40449c); in gf100_gr_trap_intr()
1484 nvkm_wr32(device, 0x404490, 0xc0000000); in gf100_gr_trap_intr()
1485 nvkm_wr32(device, 0x400108, 0x00000080); in gf100_gr_trap_intr()
1490 u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff; in gf100_gr_trap_intr()
1496 nvkm_wr32(device, 0x407020, 0x40000000); in gf100_gr_trap_intr()
1497 nvkm_wr32(device, 0x400108, 0x00000100); in gf100_gr_trap_intr()
1502 u32 stat = nvkm_rd32(device, 0x400118); in gf100_gr_trap_intr()
1507 nvkm_wr32(device, 0x400118, mask); in gf100_gr_trap_intr()
1511 nvkm_wr32(device, 0x400108, 0x01000000); in gf100_gr_trap_intr()
1517 u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); in gf100_gr_trap_intr()
1518 u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); in gf100_gr_trap_intr()
1521 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); in gf100_gr_trap_intr()
1522 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); in gf100_gr_trap_intr()
1524 nvkm_wr32(device, 0x400108, 0x02000000); in gf100_gr_trap_intr()
1530 nvkm_wr32(device, 0x400108, trap); in gf100_gr_trap_intr()
1538 struct nvkm_device *device = subdev->device; in gf100_gr_ctxctl_debug_unit() local
1540 nvkm_rd32(device, base + 0x400)); in gf100_gr_ctxctl_debug_unit()
1542 nvkm_rd32(device, base + 0x800), in gf100_gr_ctxctl_debug_unit()
1543 nvkm_rd32(device, base + 0x804), in gf100_gr_ctxctl_debug_unit()
1544 nvkm_rd32(device, base + 0x808), in gf100_gr_ctxctl_debug_unit()
1545 nvkm_rd32(device, base + 0x80c)); in gf100_gr_ctxctl_debug_unit()
1547 nvkm_rd32(device, base + 0x810), in gf100_gr_ctxctl_debug_unit()
1548 nvkm_rd32(device, base + 0x814), in gf100_gr_ctxctl_debug_unit()
1549 nvkm_rd32(device, base + 0x818), in gf100_gr_ctxctl_debug_unit()
1550 nvkm_rd32(device, base + 0x81c)); in gf100_gr_ctxctl_debug_unit()
1556 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_ctxctl_debug() local
1557 u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff; in gf100_gr_ctxctl_debug()
1569 struct nvkm_device *device = subdev->device; in gf100_gr_ctxctl_isr() local
1570 u32 stat = nvkm_rd32(device, 0x409c18); in gf100_gr_ctxctl_isr()
1573 u32 code = nvkm_rd32(device, 0x409814); in gf100_gr_ctxctl_isr()
1575 u32 class = nvkm_rd32(device, 0x409808); in gf100_gr_ctxctl_isr()
1576 u32 addr = nvkm_rd32(device, 0x40980c); in gf100_gr_ctxctl_isr()
1579 u32 data = nvkm_rd32(device, 0x409810); in gf100_gr_ctxctl_isr()
1587 nvkm_wr32(device, 0x409c20, 0x00000001); in gf100_gr_ctxctl_isr()
1594 nvkm_wr32(device, 0x409c20, 0x00080000); in gf100_gr_ctxctl_isr()
1601 nvkm_wr32(device, 0x409c20, stat); in gf100_gr_ctxctl_isr()
1610 struct nvkm_device *device = subdev->device; in gf100_gr_intr() local
1613 u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; in gf100_gr_intr()
1614 u32 stat = nvkm_rd32(device, 0x400100); in gf100_gr_intr()
1615 u32 addr = nvkm_rd32(device, 0x400704); in gf100_gr_intr()
1618 u32 data = nvkm_rd32(device, 0x400708); in gf100_gr_intr()
1619 u32 code = nvkm_rd32(device, 0x400110); in gf100_gr_intr()
1630 if (device->card_type < NV_E0 || subc < 4) in gf100_gr_intr()
1631 class = nvkm_rd32(device, 0x404200 + (subc * 4)); in gf100_gr_intr()
1640 nvkm_wr32(device, 0x400100, 0x00000001); in gf100_gr_intr()
1645 if (!gf100_gr_mthd_sw(device, class, mthd, data)) { in gf100_gr_intr()
1651 nvkm_wr32(device, 0x400100, 0x00000010); in gf100_gr_intr()
1659 nvkm_wr32(device, 0x400100, 0x00000020); in gf100_gr_intr()
1670 nvkm_wr32(device, 0x400100, 0x00100000); in gf100_gr_intr()
1678 nvkm_wr32(device, 0x400100, 0x00200000); in gf100_gr_intr()
1684 nvkm_wr32(device, 0x400100, 0x00080000); in gf100_gr_intr()
1690 nvkm_wr32(device, 0x400100, stat); in gf100_gr_intr()
1693 nvkm_wr32(device, 0x400500, 0x00010001); in gf100_gr_intr()
1711 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_csdata() local
1717 nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar); in gf100_gr_init_csdata()
1718 star = nvkm_rd32(device, falcon + 0x01c4); in gf100_gr_init_csdata()
1719 temp = nvkm_rd32(device, falcon + 0x01c4); in gf100_gr_init_csdata()
1722 nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star); in gf100_gr_init_csdata()
1731 nvkm_wr32(device, falcon + 0x01c4, data); in gf100_gr_init_csdata()
1743 nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr); in gf100_gr_init_csdata()
1744 nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar); in gf100_gr_init_csdata()
1745 nvkm_wr32(device, falcon + 0x01c4, star + 4); in gf100_gr_init_csdata()
1753 struct nvkm_device *device = subdev->device; in gf100_gr_init_ctxctl_ext() local
1758 nvkm_mc_unk260(device, 0); in gf100_gr_init_ctxctl_ext()
1762 if (!nvkm_acr_managed_falcon(device, NVKM_ACR_LSF_FECS)) { in gf100_gr_init_ctxctl_ext()
1769 if (!nvkm_acr_managed_falcon(device, NVKM_ACR_LSF_GPCCS)) { in gf100_gr_init_ctxctl_ext()
1777 ret = nvkm_acr_bootstrap_falcons(device, lsf_mask); in gf100_gr_init_ctxctl_ext()
1782 nvkm_mc_unk260(device, 1); in gf100_gr_init_ctxctl_ext()
1785 nvkm_wr32(device, 0x409800, 0x00000000); in gf100_gr_init_ctxctl_ext()
1786 nvkm_wr32(device, 0x41a10c, 0x00000000); in gf100_gr_init_ctxctl_ext()
1787 nvkm_wr32(device, 0x40910c, 0x00000000); in gf100_gr_init_ctxctl_ext()
1792 if (nvkm_msec(device, 2000, in gf100_gr_init_ctxctl_ext()
1793 if (nvkm_rd32(device, 0x409800) & 0x00000001) in gf100_gr_init_ctxctl_ext()
1835 struct nvkm_device *device = subdev->device; in gf100_gr_init_ctxctl_int() local
1842 nvkm_mc_unk260(device, 0); in gf100_gr_init_ctxctl_int()
1857 nvkm_mc_unk260(device, 1); in gf100_gr_init_ctxctl_int()
1867 nvkm_wr32(device, 0x40910c, 0x00000000); in gf100_gr_init_ctxctl_int()
1868 nvkm_wr32(device, 0x409100, 0x00000002); in gf100_gr_init_ctxctl_int()
1869 if (nvkm_msec(device, 2000, in gf100_gr_init_ctxctl_int()
1870 if (nvkm_rd32(device, 0x409800) & 0x80000000) in gf100_gr_init_ctxctl_int()
1877 gr->size = nvkm_rd32(device, 0x409804); in gf100_gr_init_ctxctl_int()
1993 struct nvkm_device *device = subdev->device; in gf100_gr_oneinit() local
1994 struct nvkm_intr *intr = &device->mc->intr; in gf100_gr_oneinit()
2006 nvkm_pmu_pgob(device->pmu, false); in gf100_gr_oneinit()
2009 gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; in gf100_gr_oneinit()
2011 gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); in gf100_gr_oneinit()
2016 nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); in gf100_gr_oneinit()
2035 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->pagepool_size, in gf100_gr_oneinit()
2040 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->bundle_size, in gf100_gr_oneinit()
2045 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->attrib_cb_size(gr), in gf100_gr_oneinit()
2051 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->unknown_size, in gf100_gr_oneinit()
2068 struct nvkm_device *device = subdev->device; in gf100_gr_init_() local
2069 bool reset = device->chipset == 0x137 || device->chipset == 0x138; in gf100_gr_init_()
2087 reset = nvkm_boolopt(device->cfgopt, "NvGrResetWar", reset); in gf100_gr_init_()
2089 nvkm_mask(device, 0x000200, 0x00001000, 0x00000000); in gf100_gr_init_()
2090 nvkm_rd32(device, 0x000200); in gf100_gr_init_()
2092 nvkm_mask(device, 0x000200, 0x00001000, 0x00001000); in gf100_gr_init_()
2093 nvkm_rd32(device, 0x000200); in gf100_gr_init_()
2096 nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); in gf100_gr_init_()
2171 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_num_tpc_per_gpc() local
2179 nvkm_wr32(device, 0x406028 + (i * 4), data); in gf100_gr_init_num_tpc_per_gpc()
2181 nvkm_wr32(device, 0x405870 + (i * 4), data); in gf100_gr_init_num_tpc_per_gpc()
2188 nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x34ce3464); in gf100_gr_init_400054()
2194 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_exception2() local
2196 nvkm_wr32(device, 0x40011c, 0xffffffff); in gf100_gr_init_exception2()
2197 nvkm_wr32(device, 0x400134, 0xffffffff); in gf100_gr_init_exception2()
2203 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_rop_exceptions() local
2207 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000); in gf100_gr_init_rop_exceptions()
2208 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000); in gf100_gr_init_rop_exceptions()
2209 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); in gf100_gr_init_rop_exceptions()
2210 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); in gf100_gr_init_rop_exceptions()
2217 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_shader_exceptions() local
2218 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); in gf100_gr_init_shader_exceptions()
2219 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); in gf100_gr_init_shader_exceptions()
2225 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_tex_hww_esr() local
2226 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); in gf100_gr_init_tex_hww_esr()
2232 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_419eb4() local
2233 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); in gf100_gr_init_419eb4()
2239 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_419cc0() local
2242 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); in gf100_gr_init_419cc0()
2246 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); in gf100_gr_init_419cc0()
2253 nvkm_wr32(gr->base.engine.subdev.device, 0x40601c, 0xc0000000); in gf100_gr_init_40601c()
2260 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, data); in gf100_gr_init_fecs_exceptions()
2266 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_gpc_mmu() local
2267 struct nvkm_fb *fb = device->fb; in gf100_gr_init_gpc_mmu()
2269 nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0x00000001); in gf100_gr_init_gpc_mmu()
2270 nvkm_wr32(device, 0x4188a4, 0x03000000); in gf100_gr_init_gpc_mmu()
2271 nvkm_wr32(device, 0x418888, 0x00000000); in gf100_gr_init_gpc_mmu()
2272 nvkm_wr32(device, 0x41888c, 0x00000000); in gf100_gr_init_gpc_mmu()
2273 nvkm_wr32(device, 0x418890, 0x00000000); in gf100_gr_init_gpc_mmu()
2274 nvkm_wr32(device, 0x418894, 0x00000000); in gf100_gr_init_gpc_mmu()
2275 nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(fb->mmu_wr) >> 8); in gf100_gr_init_gpc_mmu()
2276 nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(fb->mmu_rd) >> 8); in gf100_gr_init_gpc_mmu()
2282 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_num_active_ltcs() local
2283 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); in gf100_gr_init_num_active_ltcs()
2289 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_zcull() local
2300 nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data); in gf100_gr_init_zcull()
2304 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in gf100_gr_init_zcull()
2306 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in gf100_gr_init_zcull()
2308 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in gf100_gr_init_zcull()
2311 nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); in gf100_gr_init_zcull()
2317 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init_vsc_stream_master() local
2318 nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001); in gf100_gr_init_vsc_stream_master()
2325 struct nvkm_device *device = subdev->device; in gf100_gr_reset() local
2328 nvkm_mask(device, 0x400500, 0x00000001, 0x00000000); in gf100_gr_reset()
2333 nvkm_mc_disable(device, subdev->type, subdev->inst); in gf100_gr_reset()
2337 nvkm_mc_enable(device, subdev->type, subdev->inst); in gf100_gr_reset()
2344 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_init() local
2347 nvkm_mask(device, 0x400500, 0x00010001, 0x00000000); in gf100_gr_init()
2369 nvkm_therm_clkgate_init(device->therm, gr->func->clkgate_pack); in gf100_gr_init()
2386 nvkm_wr32(device, 0x400500, 0x00010001); in gf100_gr_init()
2388 nvkm_wr32(device, 0x400100, 0xffffffff); in gf100_gr_init()
2389 nvkm_wr32(device, 0x40013c, 0xffffffff); in gf100_gr_init()
2390 nvkm_wr32(device, 0x400124, 0x00000002); in gf100_gr_init()
2400 nvkm_wr32(device, 0x404000, 0xc0000000); in gf100_gr_init()
2401 nvkm_wr32(device, 0x404600, 0xc0000000); in gf100_gr_init()
2402 nvkm_wr32(device, 0x408030, 0xc0000000); in gf100_gr_init()
2407 nvkm_wr32(device, 0x406018, 0xc0000000); in gf100_gr_init()
2408 nvkm_wr32(device, 0x404490, 0xc0000000); in gf100_gr_init()
2413 nvkm_wr32(device, 0x405840, 0xc0000000); in gf100_gr_init()
2414 nvkm_wr32(device, 0x405844, 0x00ffffff); in gf100_gr_init()
2427 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); in gf100_gr_init()
2428 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); in gf100_gr_init()
2429 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); in gf100_gr_init()
2430 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); in gf100_gr_init()
2432 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); in gf100_gr_init()
2433 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); in gf100_gr_init()
2436 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); in gf100_gr_init()
2441 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); in gf100_gr_init()
2442 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); in gf100_gr_init()
2447 nvkm_wr32(device, 0x400108, 0xffffffff); in gf100_gr_init()
2448 nvkm_wr32(device, 0x400138, 0xffffffff); in gf100_gr_init()
2449 nvkm_wr32(device, 0x400118, 0xffffffff); in gf100_gr_init()
2450 nvkm_wr32(device, 0x400130, 0xffffffff); in gf100_gr_init()
2468 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_fecs_reset() local
2470 nvkm_wr32(device, 0x409614, 0x00000070); in gf100_gr_fecs_reset()
2471 nvkm_usec(device, 10, NVKM_DELAY); in gf100_gr_fecs_reset()
2472 nvkm_mask(device, 0x409614, 0x00000700, 0x00000700); in gf100_gr_fecs_reset()
2473 nvkm_usec(device, 10, NVKM_DELAY); in gf100_gr_fecs_reset()
2474 nvkm_rd32(device, 0x409614); in gf100_gr_fecs_reset()
2572 struct nvkm_device *device = subdev->device; in gf100_gr_load_fw() local
2577 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, name); in gf100_gr_load_fw()
2578 ret = request_firmware(&fw, f, device->dev); in gf100_gr_load_fw()
2581 ret = request_firmware(&fw, f, device->dev); in gf100_gr_load_fw()
2597 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_load() local
2599 if (!nvkm_boolopt(device->cfgopt, "NvGrUseFW", false)) in gf100_gr_load()
2620 gf100_gr_new_(const struct gf100_gr_fwif *fwif, struct nvkm_device *device, in gf100_gr_new_() argument
2630 ret = nvkm_gr_ctor(&gf100_gr_, device, type, inst, true, &gr->base); in gf100_gr_new_()
2656 gf100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) in gf100_gr_new() argument
2658 return gf100_gr_new_(gf100_gr_fwif, device, type, inst, pgr); in gf100_gr_new()