Lines Matching refs:device
120 nv40_gr_vs_count(struct nvkm_device *device) in nv40_gr_vs_count() argument
123 switch (device->chipset) { in nv40_gr_vs_count()
161 struct nvkm_device *device = ctx->device; in nv40_gr_construct_general() local
188 if (device->chipset == 0x40) { in nv40_gr_construct_general()
209 if (nv44_gr_class(ctx->device)) { in nv40_gr_construct_general()
218 if (!nv44_gr_class(ctx->device)) { in nv40_gr_construct_general()
224 if (device->chipset == 0x4c || in nv40_gr_construct_general()
225 (device->chipset & 0xf0) == 0x60) in nv40_gr_construct_general()
232 switch (device->chipset) { in nv40_gr_construct_general()
241 switch (device->chipset) { in nv40_gr_construct_general()
267 struct nvkm_device *device = ctx->device; in nv40_gr_construct_state3d() local
270 if (device->chipset == 0x40) { in nv40_gr_construct_state3d()
274 if (device->chipset == 0x46 || device->chipset == 0x47 || in nv40_gr_construct_state3d()
275 device->chipset == 0x49 || device->chipset == 0x4b) { in nv40_gr_construct_state3d()
279 if (device->chipset == 0x46) in nv40_gr_construct_state3d()
290 if (device->chipset == 0x40) { in nv40_gr_construct_state3d()
298 switch (device->chipset) { in nv40_gr_construct_state3d()
317 if (device->chipset == 0x40) { in nv40_gr_construct_state3d()
328 cp_ctx(ctx, 0x401b10, device->chipset == 0x40 ? 2 : 1); in nv40_gr_construct_state3d()
330 cp_ctx(ctx, 0x401b18, device->chipset == 0x40 ? 6 : 5); in nv40_gr_construct_state3d()
331 gr_def(ctx, 0x401b28, device->chipset == 0x40 ? in nv40_gr_construct_state3d()
342 if (device->chipset != 0x44 && device->chipset != 0x4a && in nv40_gr_construct_state3d()
343 device->chipset != 0x4e) in nv40_gr_construct_state3d()
372 struct nvkm_device *device = ctx->device; in nv40_gr_construct_state3d_2() local
376 cp_ctx(ctx, 0x402404, device->chipset == 0x40 ? 1 : 2); in nv40_gr_construct_state3d_2()
377 switch (device->chipset) { in nv40_gr_construct_state3d_2()
394 if (device->chipset != 0x40) in nv40_gr_construct_state3d_2()
396 switch (device->chipset) { in nv40_gr_construct_state3d_2()
409 cp_ctx(ctx, 0x402480, device->chipset == 0x40 ? 8 : 9); in nv40_gr_construct_state3d_2()
412 switch (device->chipset) { in nv40_gr_construct_state3d_2()
429 gr_def(ctx, 0x40249c, device->chipset <= 0x43 ? in nv40_gr_construct_state3d_2()
433 if (device->chipset == 0x40) in nv40_gr_construct_state3d_2()
438 switch (device->chipset) { in nv40_gr_construct_state3d_2()
446 if (device->chipset != 0x47) { /* belong at end!! */ in nv40_gr_construct_state3d_2()
471 gr_def(ctx, 0x402c00, device->chipset == 0x40 ? in nv40_gr_construct_state3d_2()
473 switch (device->chipset) { in nv40_gr_construct_state3d_2()
486 if (device->chipset == 0x40) in nv40_gr_construct_state3d_2()
489 if (device->chipset <= 0x42) in nv40_gr_construct_state3d_2()
492 if (device->chipset <= 0x4a) in nv40_gr_construct_state3d_2()
496 cp_ctx(ctx, 0x402cb0, device->chipset == 0x40 ? 12 : 13); in nv40_gr_construct_state3d_2()
498 if (device->chipset != 0x40) in nv40_gr_construct_state3d_2()
503 cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3); in nv40_gr_construct_state3d_2()
504 cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3); in nv40_gr_construct_state3d_2()
505 cp_ctx(ctx, 0x403420, nv40_gr_vs_count(ctx->device)); in nv40_gr_construct_state3d_2()
506 for (i = 0; i < nv40_gr_vs_count(ctx->device); i++) in nv40_gr_construct_state3d_2()
509 if (device->chipset != 0x40) { in nv40_gr_construct_state3d_2()
517 switch (device->chipset) { in nv40_gr_construct_state3d_2()
528 if (device->chipset != 0x4e) in nv40_gr_construct_state3d_2()
536 int len = nv44_gr_class(ctx->device) ? 0x0084 : 0x0684; in nv40_gr_construct_state3d_3()
551 struct nvkm_device *device = ctx->device; in nv40_gr_construct_shader() local
556 vs_nr = nv40_gr_vs_count(ctx->device); in nv40_gr_construct_shader()
558 vs_nr_b1 = device->chipset == 0x40 ? 128 : 64; in nv40_gr_construct_shader()
559 if (device->chipset == 0x40) { in nv40_gr_construct_shader()
564 if (device->chipset == 0x41 || device->chipset == 0x42) { in nv40_gr_construct_shader()
571 vs_len = nv44_gr_class(device) ? 0x4980/4 : 0x4a40/4; in nv40_gr_construct_shader()
575 cp_out(ctx, nv44_gr_class(device) ? 0x800029 : 0x800041); in nv40_gr_construct_shader()
661 nv40_grctx_fill(struct nvkm_device *device, struct nvkm_gpuobj *mem) in nv40_grctx_fill() argument
664 .device = device, in nv40_grctx_fill()
671 nv40_grctx_init(struct nvkm_device *device, u32 *size) in nv40_grctx_init() argument
675 .device = device, in nv40_grctx_init()
686 nvkm_wr32(device, 0x400324, 0); in nv40_grctx_init()
688 nvkm_wr32(device, 0x400328, ctxprog[i]); in nv40_grctx_init()