Lines Matching refs:ctx
159 nv40_gr_construct_general(struct nvkm_grctx *ctx) in nv40_gr_construct_general() argument
161 struct nvkm_device *device = ctx->device; in nv40_gr_construct_general()
164 cp_ctx(ctx, 0x4000a4, 1); in nv40_gr_construct_general()
165 gr_def(ctx, 0x4000a4, 0x00000008); in nv40_gr_construct_general()
166 cp_ctx(ctx, 0x400144, 58); in nv40_gr_construct_general()
167 gr_def(ctx, 0x400144, 0x00000001); in nv40_gr_construct_general()
168 cp_ctx(ctx, 0x400314, 1); in nv40_gr_construct_general()
169 gr_def(ctx, 0x400314, 0x00000000); in nv40_gr_construct_general()
170 cp_ctx(ctx, 0x400400, 10); in nv40_gr_construct_general()
171 cp_ctx(ctx, 0x400480, 10); in nv40_gr_construct_general()
172 cp_ctx(ctx, 0x400500, 19); in nv40_gr_construct_general()
173 gr_def(ctx, 0x400514, 0x00040000); in nv40_gr_construct_general()
174 gr_def(ctx, 0x400524, 0x55555555); in nv40_gr_construct_general()
175 gr_def(ctx, 0x400528, 0x55555555); in nv40_gr_construct_general()
176 gr_def(ctx, 0x40052c, 0x55555555); in nv40_gr_construct_general()
177 gr_def(ctx, 0x400530, 0x55555555); in nv40_gr_construct_general()
178 cp_ctx(ctx, 0x400560, 6); in nv40_gr_construct_general()
179 gr_def(ctx, 0x400568, 0x0000ffff); in nv40_gr_construct_general()
180 gr_def(ctx, 0x40056c, 0x0000ffff); in nv40_gr_construct_general()
181 cp_ctx(ctx, 0x40057c, 5); in nv40_gr_construct_general()
182 cp_ctx(ctx, 0x400710, 3); in nv40_gr_construct_general()
183 gr_def(ctx, 0x400710, 0x20010001); in nv40_gr_construct_general()
184 gr_def(ctx, 0x400714, 0x0f73ef00); in nv40_gr_construct_general()
185 cp_ctx(ctx, 0x400724, 1); in nv40_gr_construct_general()
186 gr_def(ctx, 0x400724, 0x02008821); in nv40_gr_construct_general()
187 cp_ctx(ctx, 0x400770, 3); in nv40_gr_construct_general()
189 cp_ctx(ctx, 0x400814, 4); in nv40_gr_construct_general()
190 cp_ctx(ctx, 0x400828, 5); in nv40_gr_construct_general()
191 cp_ctx(ctx, 0x400840, 5); in nv40_gr_construct_general()
192 gr_def(ctx, 0x400850, 0x00000040); in nv40_gr_construct_general()
193 cp_ctx(ctx, 0x400858, 4); in nv40_gr_construct_general()
194 gr_def(ctx, 0x400858, 0x00000040); in nv40_gr_construct_general()
195 gr_def(ctx, 0x40085c, 0x00000040); in nv40_gr_construct_general()
196 gr_def(ctx, 0x400864, 0x80000000); in nv40_gr_construct_general()
197 cp_ctx(ctx, 0x40086c, 9); in nv40_gr_construct_general()
198 gr_def(ctx, 0x40086c, 0x80000000); in nv40_gr_construct_general()
199 gr_def(ctx, 0x400870, 0x80000000); in nv40_gr_construct_general()
200 gr_def(ctx, 0x400874, 0x80000000); in nv40_gr_construct_general()
201 gr_def(ctx, 0x400878, 0x80000000); in nv40_gr_construct_general()
202 gr_def(ctx, 0x400888, 0x00000040); in nv40_gr_construct_general()
203 gr_def(ctx, 0x40088c, 0x80000000); in nv40_gr_construct_general()
204 cp_ctx(ctx, 0x4009c0, 8); in nv40_gr_construct_general()
205 gr_def(ctx, 0x4009cc, 0x80000000); in nv40_gr_construct_general()
206 gr_def(ctx, 0x4009dc, 0x80000000); in nv40_gr_construct_general()
208 cp_ctx(ctx, 0x400840, 20); in nv40_gr_construct_general()
209 if (nv44_gr_class(ctx->device)) { in nv40_gr_construct_general()
211 gr_def(ctx, 0x400860 + (i * 4), 0x00000001); in nv40_gr_construct_general()
213 gr_def(ctx, 0x400880, 0x00000040); in nv40_gr_construct_general()
214 gr_def(ctx, 0x400884, 0x00000040); in nv40_gr_construct_general()
215 gr_def(ctx, 0x400888, 0x00000040); in nv40_gr_construct_general()
216 cp_ctx(ctx, 0x400894, 11); in nv40_gr_construct_general()
217 gr_def(ctx, 0x400894, 0x00000040); in nv40_gr_construct_general()
218 if (!nv44_gr_class(ctx->device)) { in nv40_gr_construct_general()
220 gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000); in nv40_gr_construct_general()
222 cp_ctx(ctx, 0x4008e0, 2); in nv40_gr_construct_general()
223 cp_ctx(ctx, 0x4008f8, 2); in nv40_gr_construct_general()
226 cp_ctx(ctx, 0x4009f8, 1); in nv40_gr_construct_general()
228 cp_ctx(ctx, 0x400a00, 73); in nv40_gr_construct_general()
229 gr_def(ctx, 0x400b0c, 0x0b0b0b0c); in nv40_gr_construct_general()
230 cp_ctx(ctx, 0x401000, 4); in nv40_gr_construct_general()
231 cp_ctx(ctx, 0x405004, 1); in nv40_gr_construct_general()
236 cp_ctx(ctx, 0x403448, 1); in nv40_gr_construct_general()
237 gr_def(ctx, 0x403448, 0x00001010); in nv40_gr_construct_general()
240 cp_ctx(ctx, 0x403440, 1); in nv40_gr_construct_general()
243 gr_def(ctx, 0x403440, 0x00000010); in nv40_gr_construct_general()
248 gr_def(ctx, 0x403440, 0x00003010); in nv40_gr_construct_general()
257 gr_def(ctx, 0x403440, 0x00001010); in nv40_gr_construct_general()
265 nv40_gr_construct_state3d(struct nvkm_grctx *ctx) in nv40_gr_construct_state3d() argument
267 struct nvkm_device *device = ctx->device; in nv40_gr_construct_state3d()
271 cp_ctx(ctx, 0x401880, 51); in nv40_gr_construct_state3d()
272 gr_def(ctx, 0x401940, 0x00000100); in nv40_gr_construct_state3d()
276 cp_ctx(ctx, 0x401880, 32); in nv40_gr_construct_state3d()
278 gr_def(ctx, 0x401880 + (i * 4), 0x00000111); in nv40_gr_construct_state3d()
280 cp_ctx(ctx, 0x401900, 16); in nv40_gr_construct_state3d()
281 cp_ctx(ctx, 0x401940, 3); in nv40_gr_construct_state3d()
283 cp_ctx(ctx, 0x40194c, 18); in nv40_gr_construct_state3d()
284 gr_def(ctx, 0x401954, 0x00000111); in nv40_gr_construct_state3d()
285 gr_def(ctx, 0x401958, 0x00080060); in nv40_gr_construct_state3d()
286 gr_def(ctx, 0x401974, 0x00000080); in nv40_gr_construct_state3d()
287 gr_def(ctx, 0x401978, 0xffff0000); in nv40_gr_construct_state3d()
288 gr_def(ctx, 0x40197c, 0x00000001); in nv40_gr_construct_state3d()
289 gr_def(ctx, 0x401990, 0x46400000); in nv40_gr_construct_state3d()
291 cp_ctx(ctx, 0x4019a0, 2); in nv40_gr_construct_state3d()
292 cp_ctx(ctx, 0x4019ac, 5); in nv40_gr_construct_state3d()
294 cp_ctx(ctx, 0x4019a0, 1); in nv40_gr_construct_state3d()
295 cp_ctx(ctx, 0x4019b4, 3); in nv40_gr_construct_state3d()
297 gr_def(ctx, 0x4019bc, 0xffff0000); in nv40_gr_construct_state3d()
303 cp_ctx(ctx, 0x4019c0, 18); in nv40_gr_construct_state3d()
305 gr_def(ctx, 0x4019c0 + (i * 4), 0x88888888); in nv40_gr_construct_state3d()
308 cp_ctx(ctx, 0x401a08, 8); in nv40_gr_construct_state3d()
309 gr_def(ctx, 0x401a10, 0x0fff0000); in nv40_gr_construct_state3d()
310 gr_def(ctx, 0x401a14, 0x0fff0000); in nv40_gr_construct_state3d()
311 gr_def(ctx, 0x401a1c, 0x00011100); in nv40_gr_construct_state3d()
312 cp_ctx(ctx, 0x401a2c, 4); in nv40_gr_construct_state3d()
313 cp_ctx(ctx, 0x401a44, 26); in nv40_gr_construct_state3d()
315 gr_def(ctx, 0x401a44 + (i * 4), 0x07ff0000); in nv40_gr_construct_state3d()
316 gr_def(ctx, 0x401a8c, 0x4b7fffff); in nv40_gr_construct_state3d()
318 cp_ctx(ctx, 0x401ab8, 3); in nv40_gr_construct_state3d()
320 cp_ctx(ctx, 0x401ab8, 1); in nv40_gr_construct_state3d()
321 cp_ctx(ctx, 0x401ac0, 1); in nv40_gr_construct_state3d()
323 cp_ctx(ctx, 0x401ad0, 8); in nv40_gr_construct_state3d()
324 gr_def(ctx, 0x401ad0, 0x30201000); in nv40_gr_construct_state3d()
325 gr_def(ctx, 0x401ad4, 0x70605040); in nv40_gr_construct_state3d()
326 gr_def(ctx, 0x401ad8, 0xb8a89888); in nv40_gr_construct_state3d()
327 gr_def(ctx, 0x401adc, 0xf8e8d8c8); in nv40_gr_construct_state3d()
328 cp_ctx(ctx, 0x401b10, device->chipset == 0x40 ? 2 : 1); in nv40_gr_construct_state3d()
329 gr_def(ctx, 0x401b10, 0x40100000); in nv40_gr_construct_state3d()
330 cp_ctx(ctx, 0x401b18, device->chipset == 0x40 ? 6 : 5); in nv40_gr_construct_state3d()
331 gr_def(ctx, 0x401b28, device->chipset == 0x40 ? in nv40_gr_construct_state3d()
333 cp_ctx(ctx, 0x401b30, 25); in nv40_gr_construct_state3d()
334 gr_def(ctx, 0x401b34, 0x0000ffff); in nv40_gr_construct_state3d()
335 gr_def(ctx, 0x401b68, 0x435185d6); in nv40_gr_construct_state3d()
336 gr_def(ctx, 0x401b6c, 0x2155b699); in nv40_gr_construct_state3d()
337 gr_def(ctx, 0x401b70, 0xfedcba98); in nv40_gr_construct_state3d()
338 gr_def(ctx, 0x401b74, 0x00000098); in nv40_gr_construct_state3d()
339 gr_def(ctx, 0x401b84, 0xffffffff); in nv40_gr_construct_state3d()
340 gr_def(ctx, 0x401b88, 0x00ff7000); in nv40_gr_construct_state3d()
341 gr_def(ctx, 0x401b8c, 0x0000ffff); in nv40_gr_construct_state3d()
344 cp_ctx(ctx, 0x401b94, 1); in nv40_gr_construct_state3d()
345 cp_ctx(ctx, 0x401b98, 8); in nv40_gr_construct_state3d()
346 gr_def(ctx, 0x401b9c, 0x00ff0000); in nv40_gr_construct_state3d()
347 cp_ctx(ctx, 0x401bc0, 9); in nv40_gr_construct_state3d()
348 gr_def(ctx, 0x401be0, 0x00ffff00); in nv40_gr_construct_state3d()
349 cp_ctx(ctx, 0x401c00, 192); in nv40_gr_construct_state3d()
351 gr_def(ctx, 0x401c40 + (i * 4), 0x00018488); in nv40_gr_construct_state3d()
352 gr_def(ctx, 0x401c80 + (i * 4), 0x00028202); in nv40_gr_construct_state3d()
353 gr_def(ctx, 0x401d00 + (i * 4), 0x0000aae4); in nv40_gr_construct_state3d()
354 gr_def(ctx, 0x401d40 + (i * 4), 0x01012000); in nv40_gr_construct_state3d()
355 gr_def(ctx, 0x401d80 + (i * 4), 0x00080008); in nv40_gr_construct_state3d()
356 gr_def(ctx, 0x401e00 + (i * 4), 0x00100008); in nv40_gr_construct_state3d()
359 gr_def(ctx, 0x401e90 + (i * 4), 0x0001bc80); in nv40_gr_construct_state3d()
360 gr_def(ctx, 0x401ea0 + (i * 4), 0x00000202); in nv40_gr_construct_state3d()
361 gr_def(ctx, 0x401ec0 + (i * 4), 0x00000008); in nv40_gr_construct_state3d()
362 gr_def(ctx, 0x401ee0 + (i * 4), 0x00080008); in nv40_gr_construct_state3d()
364 cp_ctx(ctx, 0x400f5c, 3); in nv40_gr_construct_state3d()
365 gr_def(ctx, 0x400f5c, 0x00000002); in nv40_gr_construct_state3d()
366 cp_ctx(ctx, 0x400f84, 1); in nv40_gr_construct_state3d()
370 nv40_gr_construct_state3d_2(struct nvkm_grctx *ctx) in nv40_gr_construct_state3d_2() argument
372 struct nvkm_device *device = ctx->device; in nv40_gr_construct_state3d_2()
375 cp_ctx(ctx, 0x402000, 1); in nv40_gr_construct_state3d_2()
376 cp_ctx(ctx, 0x402404, device->chipset == 0x40 ? 1 : 2); in nv40_gr_construct_state3d_2()
379 gr_def(ctx, 0x402404, 0x00000001); in nv40_gr_construct_state3d_2()
384 gr_def(ctx, 0x402404, 0x00000020); in nv40_gr_construct_state3d_2()
389 gr_def(ctx, 0x402404, 0x00000421); in nv40_gr_construct_state3d_2()
392 gr_def(ctx, 0x402404, 0x00000021); in nv40_gr_construct_state3d_2()
395 gr_def(ctx, 0x402408, 0x030c30c3); in nv40_gr_construct_state3d_2()
403 cp_ctx(ctx, 0x402440, 1); in nv40_gr_construct_state3d_2()
404 gr_def(ctx, 0x402440, 0x00011001); in nv40_gr_construct_state3d_2()
409 cp_ctx(ctx, 0x402480, device->chipset == 0x40 ? 8 : 9); in nv40_gr_construct_state3d_2()
410 gr_def(ctx, 0x402488, 0x3e020200); in nv40_gr_construct_state3d_2()
411 gr_def(ctx, 0x40248c, 0x00ffffff); in nv40_gr_construct_state3d_2()
414 gr_def(ctx, 0x402490, 0x60103f00); in nv40_gr_construct_state3d_2()
417 gr_def(ctx, 0x402490, 0x40103f00); in nv40_gr_construct_state3d_2()
423 gr_def(ctx, 0x402490, 0x20103f00); in nv40_gr_construct_state3d_2()
426 gr_def(ctx, 0x402490, 0x0c103f00); in nv40_gr_construct_state3d_2()
429 gr_def(ctx, 0x40249c, device->chipset <= 0x43 ? in nv40_gr_construct_state3d_2()
431 cp_ctx(ctx, 0x402500, 31); in nv40_gr_construct_state3d_2()
432 gr_def(ctx, 0x402530, 0x00008100); in nv40_gr_construct_state3d_2()
434 cp_ctx(ctx, 0x40257c, 6); in nv40_gr_construct_state3d_2()
435 cp_ctx(ctx, 0x402594, 16); in nv40_gr_construct_state3d_2()
436 cp_ctx(ctx, 0x402800, 17); in nv40_gr_construct_state3d_2()
437 gr_def(ctx, 0x402800, 0x00000001); in nv40_gr_construct_state3d_2()
442 cp_ctx(ctx, 0x402864, 1); in nv40_gr_construct_state3d_2()
443 gr_def(ctx, 0x402864, 0x00001001); in nv40_gr_construct_state3d_2()
444 cp_ctx(ctx, 0x402870, 3); in nv40_gr_construct_state3d_2()
445 gr_def(ctx, 0x402878, 0x00000003); in nv40_gr_construct_state3d_2()
447 cp_ctx(ctx, 0x402900, 1); in nv40_gr_construct_state3d_2()
448 cp_ctx(ctx, 0x402940, 1); in nv40_gr_construct_state3d_2()
449 cp_ctx(ctx, 0x402980, 1); in nv40_gr_construct_state3d_2()
450 cp_ctx(ctx, 0x4029c0, 1); in nv40_gr_construct_state3d_2()
451 cp_ctx(ctx, 0x402a00, 1); in nv40_gr_construct_state3d_2()
452 cp_ctx(ctx, 0x402a40, 1); in nv40_gr_construct_state3d_2()
453 cp_ctx(ctx, 0x402a80, 1); in nv40_gr_construct_state3d_2()
454 cp_ctx(ctx, 0x402ac0, 1); in nv40_gr_construct_state3d_2()
458 cp_ctx(ctx, 0x402844, 1); in nv40_gr_construct_state3d_2()
459 gr_def(ctx, 0x402844, 0x00000001); in nv40_gr_construct_state3d_2()
460 cp_ctx(ctx, 0x402850, 1); in nv40_gr_construct_state3d_2()
463 cp_ctx(ctx, 0x402844, 1); in nv40_gr_construct_state3d_2()
464 gr_def(ctx, 0x402844, 0x00001001); in nv40_gr_construct_state3d_2()
465 cp_ctx(ctx, 0x402850, 2); in nv40_gr_construct_state3d_2()
466 gr_def(ctx, 0x402854, 0x00000003); in nv40_gr_construct_state3d_2()
470 cp_ctx(ctx, 0x402c00, 4); in nv40_gr_construct_state3d_2()
471 gr_def(ctx, 0x402c00, device->chipset == 0x40 ? in nv40_gr_construct_state3d_2()
477 cp_ctx(ctx, 0x402c20, 40); in nv40_gr_construct_state3d_2()
479 gr_def(ctx, 0x402c40 + (i * 4), 0xffffffff); in nv40_gr_construct_state3d_2()
480 cp_ctx(ctx, 0x4030b8, 13); in nv40_gr_construct_state3d_2()
481 gr_def(ctx, 0x4030dc, 0x00000005); in nv40_gr_construct_state3d_2()
482 gr_def(ctx, 0x4030e8, 0x0000ffff); in nv40_gr_construct_state3d_2()
485 cp_ctx(ctx, 0x402c10, 4); in nv40_gr_construct_state3d_2()
487 cp_ctx(ctx, 0x402c20, 36); in nv40_gr_construct_state3d_2()
490 cp_ctx(ctx, 0x402c20, 24); in nv40_gr_construct_state3d_2()
493 cp_ctx(ctx, 0x402c20, 16); in nv40_gr_construct_state3d_2()
495 cp_ctx(ctx, 0x402c20, 8); in nv40_gr_construct_state3d_2()
496 cp_ctx(ctx, 0x402cb0, device->chipset == 0x40 ? 12 : 13); in nv40_gr_construct_state3d_2()
497 gr_def(ctx, 0x402cd4, 0x00000005); in nv40_gr_construct_state3d_2()
499 gr_def(ctx, 0x402ce0, 0x0000ffff); in nv40_gr_construct_state3d_2()
503 cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3); in nv40_gr_construct_state3d_2()
504 cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3); in nv40_gr_construct_state3d_2()
505 cp_ctx(ctx, 0x403420, nv40_gr_vs_count(ctx->device)); in nv40_gr_construct_state3d_2()
506 for (i = 0; i < nv40_gr_vs_count(ctx->device); i++) in nv40_gr_construct_state3d_2()
507 gr_def(ctx, 0x403420 + (i * 4), 0x00005555); in nv40_gr_construct_state3d_2()
510 cp_ctx(ctx, 0x403600, 1); in nv40_gr_construct_state3d_2()
511 gr_def(ctx, 0x403600, 0x00000001); in nv40_gr_construct_state3d_2()
513 cp_ctx(ctx, 0x403800, 1); in nv40_gr_construct_state3d_2()
515 cp_ctx(ctx, 0x403c18, 1); in nv40_gr_construct_state3d_2()
516 gr_def(ctx, 0x403c18, 0x00000001); in nv40_gr_construct_state3d_2()
522 cp_ctx(ctx, 0x405018, 1); in nv40_gr_construct_state3d_2()
523 gr_def(ctx, 0x405018, 0x08e00001); in nv40_gr_construct_state3d_2()
524 cp_ctx(ctx, 0x405c24, 1); in nv40_gr_construct_state3d_2()
525 gr_def(ctx, 0x405c24, 0x000e3000); in nv40_gr_construct_state3d_2()
529 cp_ctx(ctx, 0x405800, 11); in nv40_gr_construct_state3d_2()
530 cp_ctx(ctx, 0x407000, 1); in nv40_gr_construct_state3d_2()
534 nv40_gr_construct_state3d_3(struct nvkm_grctx *ctx) in nv40_gr_construct_state3d_3() argument
536 int len = nv44_gr_class(ctx->device) ? 0x0084 : 0x0684; in nv40_gr_construct_state3d_3()
538 cp_out (ctx, 0x300000); in nv40_gr_construct_state3d_3()
539 cp_lsr (ctx, len - 4); in nv40_gr_construct_state3d_3()
540 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_swap_state3d_3_is_save); in nv40_gr_construct_state3d_3()
541 cp_lsr (ctx, len); in nv40_gr_construct_state3d_3()
542 cp_name(ctx, cp_swap_state3d_3_is_save); in nv40_gr_construct_state3d_3()
543 cp_out (ctx, 0x800001); in nv40_gr_construct_state3d_3()
545 ctx->ctxvals_pos += len; in nv40_gr_construct_state3d_3()
549 nv40_gr_construct_shader(struct nvkm_grctx *ctx) in nv40_gr_construct_shader() argument
551 struct nvkm_device *device = ctx->device; in nv40_gr_construct_shader()
552 struct nvkm_gpuobj *obj = ctx->data; in nv40_gr_construct_shader()
556 vs_nr = nv40_gr_vs_count(ctx->device); in nv40_gr_construct_shader()
574 cp_lsr(ctx, vs_len * vs_nr + 0x300/4); in nv40_gr_construct_shader()
575 cp_out(ctx, nv44_gr_class(device) ? 0x800029 : 0x800041); in nv40_gr_construct_shader()
577 offset = ctx->ctxvals_pos; in nv40_gr_construct_shader()
578 ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len)); in nv40_gr_construct_shader()
580 if (ctx->mode != NVKM_GRCTX_VALS) in nv40_gr_construct_shader()
596 nv40_grctx_generate(struct nvkm_grctx *ctx) in nv40_grctx_generate() argument
599 cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); in nv40_grctx_generate()
600 cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); in nv40_grctx_generate()
602 cp_name(ctx, cp_check_load); in nv40_grctx_generate()
603 cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); in nv40_grctx_generate()
604 cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); in nv40_grctx_generate()
605 cp_bra (ctx, ALWAYS, TRUE, cp_exit); in nv40_grctx_generate()
608 cp_name(ctx, cp_setup_auto_load); in nv40_grctx_generate()
609 cp_wait(ctx, STATUS, IDLE); in nv40_grctx_generate()
610 cp_out (ctx, CP_NEXT_TO_SWAP); in nv40_grctx_generate()
611 cp_name(ctx, cp_setup_load); in nv40_grctx_generate()
612 cp_wait(ctx, STATUS, IDLE); in nv40_grctx_generate()
613 cp_set (ctx, SWAP_DIRECTION, LOAD); in nv40_grctx_generate()
614 cp_out (ctx, 0x00910880); /* ?? */ in nv40_grctx_generate()
615 cp_out (ctx, 0x00901ffe); /* ?? */ in nv40_grctx_generate()
616 cp_out (ctx, 0x01940000); /* ?? */ in nv40_grctx_generate()
617 cp_lsr (ctx, 0x20); in nv40_grctx_generate()
618 cp_out (ctx, 0x0060000b); /* ?? */ in nv40_grctx_generate()
619 cp_wait(ctx, UNK57, CLEAR); in nv40_grctx_generate()
620 cp_out (ctx, 0x0060000c); /* ?? */ in nv40_grctx_generate()
621 cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); in nv40_grctx_generate()
624 cp_name(ctx, cp_setup_save); in nv40_grctx_generate()
625 cp_set (ctx, SWAP_DIRECTION, SAVE); in nv40_grctx_generate()
628 cp_name(ctx, cp_swap_state); in nv40_grctx_generate()
629 cp_pos (ctx, 0x00020/4); in nv40_grctx_generate()
630 nv40_gr_construct_general(ctx); in nv40_grctx_generate()
631 cp_wait(ctx, STATUS, IDLE); in nv40_grctx_generate()
634 cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit); in nv40_grctx_generate()
635 nv40_gr_construct_state3d(ctx); in nv40_grctx_generate()
636 cp_wait(ctx, STATUS, IDLE); in nv40_grctx_generate()
639 nv40_gr_construct_state3d_2(ctx); in nv40_grctx_generate()
642 nv40_gr_construct_state3d_3(ctx); in nv40_grctx_generate()
645 cp_pos (ctx, ctx->ctxvals_pos); in nv40_grctx_generate()
646 nv40_gr_construct_shader(ctx); in nv40_grctx_generate()
649 cp_name(ctx, cp_prepare_exit); in nv40_grctx_generate()
650 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); in nv40_grctx_generate()
651 cp_bra (ctx, USER_SAVE, PENDING, cp_exit); in nv40_grctx_generate()
652 cp_out (ctx, CP_NEXT_TO_CURRENT); in nv40_grctx_generate()
654 cp_name(ctx, cp_exit); in nv40_grctx_generate()
655 cp_set (ctx, USER_SAVE, NOT_PENDING); in nv40_grctx_generate()
656 cp_set (ctx, USER_LOAD, NOT_PENDING); in nv40_grctx_generate()
657 cp_out (ctx, CP_END); in nv40_grctx_generate()
674 struct nvkm_grctx ctx = { in nv40_grctx_init() local
684 nv40_grctx_generate(&ctx); in nv40_grctx_init()
687 for (i = 0; i < ctx.ctxprog_len; i++) in nv40_grctx_init()
689 *size = ctx.ctxvals_pos * 4; in nv40_grctx_init()