37 void NVWriteVgaSeq(struct drm_device *, int head, uint8_t index, uint8_t value);
38 uint8_t NVReadVgaSeq(struct drm_device *, int head, uint8_t index);
39 void NVWriteVgaGr(struct drm_device *, int head, uint8_t index, uint8_t value);
40 uint8_t NVReadVgaGr(struct drm_device *, int head, uint8_t index);
42 void NVBlankScreen(struct drm_device *, int head, bool blank);
48 void nouveau_hw_save_state(struct drm_device *, int head,
50 void nouveau_hw_load_state(struct drm_device *, int head,
52 void nouveau_hw_load_state_palette(struct drm_device *, int head,
60 					int head, uint32_t reg)  in NVReadCRTC()  argument
64 	if (head)  in NVReadCRTC()
71 					int head, uint32_t reg, uint32_t val)  in NVWriteCRTC()  argument
74 	if (head)  in NVWriteCRTC()
80 					int head, uint32_t reg)  in NVReadRAMDAC()  argument
84 	if (head)  in NVReadRAMDAC()
91 					int head, uint32_t reg, uint32_t val)  in NVWriteRAMDAC()  argument
94 	if (head)  in NVWriteRAMDAC()
120 					int head, uint8_t index, uint8_t value)  in NVWriteVgaCrtc()  argument
123 	nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);  in NVWriteVgaCrtc()
124 	nvif_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);  in NVWriteVgaCrtc()
128 					int head, uint8_t index)  in NVReadVgaCrtc()  argument
132 	nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);  in NVReadVgaCrtc()
133 	val = nvif_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);  in NVReadVgaCrtc()
139  * per-head variables around
152 NVWriteVgaCrtc5758(struct drm_device *dev, int head, uint8_t index, uint8_t value)  in NVWriteVgaCrtc5758()  argument
154 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index);  in NVWriteVgaCrtc5758()
155 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_58, value);  in NVWriteVgaCrtc5758()
158 static inline uint8_t NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_t index)  in NVReadVgaCrtc5758()  argument
160 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index);  in NVReadVgaCrtc5758()
161 	return NVReadVgaCrtc(dev, head, NV_CIO_CRE_58);  in NVReadVgaCrtc5758()
165 					int head, uint32_t reg)  in NVReadPRMVIO()  argument
172 	 * NVSetOwner for the relevant head to be programmed */  in NVReadPRMVIO()
173 	if (head && drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)  in NVReadPRMVIO()
181 					int head, uint32_t reg, uint8_t value)  in NVWritePRMVIO()  argument
187 	 * NVSetOwner for the relevant head to be programmed */  in NVWritePRMVIO()
188 	if (head && drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)  in NVWritePRMVIO()
194 static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable)  in NVSetEnablePalette()  argument
197 	nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);  in NVSetEnablePalette()
198 	nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);  in NVSetEnablePalette()
201 static inline bool NVGetEnablePalette(struct drm_device *dev, int head)  in NVGetEnablePalette()  argument
204 	nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);  in NVGetEnablePalette()
205 	return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);  in NVGetEnablePalette()
209 					int head, uint8_t index, uint8_t value)  in NVWriteVgaAttr()  argument
212 	if (NVGetEnablePalette(dev, head))  in NVWriteVgaAttr()
217 	nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);  in NVWriteVgaAttr()
218 	nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);  in NVWriteVgaAttr()
219 	nvif_wr08(device, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value);  in NVWriteVgaAttr()
223 					int head, uint8_t index)  in NVReadVgaAttr()  argument
227 	if (NVGetEnablePalette(dev, head))  in NVReadVgaAttr()
232 	nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);  in NVReadVgaAttr()
233 	nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);  in NVReadVgaAttr()
234 	val = nvif_rd08(device, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE);  in NVReadVgaAttr()
238 static inline void NVVgaSeqReset(struct drm_device *dev, int head, bool start)  in NVVgaSeqReset()  argument
240 	NVWriteVgaSeq(dev, head, NV_VIO_SR_RESET_INDEX, start ? 0x1 : 0x3);  in NVVgaSeqReset()
243 static inline void NVVgaProtect(struct drm_device *dev, int head, bool protect)  in NVVgaProtect()  argument
245 	uint8_t seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);  in NVVgaProtect()
248 		NVVgaSeqReset(dev, head, true);  in NVVgaProtect()
249 		NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);  in NVVgaProtect()
252 		NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);   /* reenable display */  in NVVgaProtect()
253 		NVVgaSeqReset(dev, head, false);  in NVVgaProtect()
255 	NVSetEnablePalette(dev, head, protect);  in NVVgaProtect()
270 /* makes cr0-7 on the specified head read-only */
272 nv_lock_vga_crtc_base(struct drm_device *dev, int head, bool lock)  in nv_lock_vga_crtc_base()  argument
274 	uint8_t cr11 = NVReadVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX);  in nv_lock_vga_crtc_base()
281 	NVWriteVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX, cr11);  in nv_lock_vga_crtc_base()
287 nv_lock_vga_crtc_shadow(struct drm_device *dev, int head, int lock)  in nv_lock_vga_crtc_shadow()  argument
303 		cr21 = NVReadVgaCrtc(dev, head, NV_CIO_CRE_21) | 0xfa;  in nv_lock_vga_crtc_shadow()
305 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_21, cr21);  in nv_lock_vga_crtc_shadow()
341 nv_fix_nv40_hw_cursor(struct drm_device *dev, int head)  in nv_fix_nv40_hw_cursor()  argument
348 	uint32_t curpos = NVReadRAMDAC(dev, head, NV_PRAMDAC_CU_START_POS);  in nv_fix_nv40_hw_cursor()
349 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_CU_START_POS, curpos);  in nv_fix_nv40_hw_cursor()
353 nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset)  in nv_set_crtc_base()  argument
357 	NVWriteCRTC(dev, head, NV_PCRTC_START, offset);  in nv_set_crtc_base()
364 		int cre_heb = NVReadVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX);  in nv_set_crtc_base()
366 		NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX,  in nv_set_crtc_base()
372 nv_show_cursor(struct drm_device *dev, int head, bool show)  in nv_show_cursor()  argument
376 		&nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];  in nv_show_cursor()
382 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1);  in nv_show_cursor()
385 		nv_fix_nv40_hw_cursor(dev, head);  in nv_show_cursor()