Lines Matching refs:dev
39 NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value) in NVWriteVgaSeq() argument
41 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); in NVWriteVgaSeq()
42 NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value); in NVWriteVgaSeq()
46 NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index) in NVReadVgaSeq() argument
48 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); in NVReadVgaSeq()
49 return NVReadPRMVIO(dev, head, NV_PRMVIO_SR); in NVReadVgaSeq()
53 NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value) in NVWriteVgaGr() argument
55 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); in NVWriteVgaGr()
56 NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value); in NVWriteVgaGr()
60 NVReadVgaGr(struct drm_device *dev, int head, uint8_t index) in NVReadVgaGr() argument
62 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); in NVReadVgaGr()
63 return NVReadPRMVIO(dev, head, NV_PRMVIO_GX); in NVReadVgaGr()
85 NVSetOwner(struct drm_device *dev, int owner) in NVSetOwner() argument
87 struct nouveau_drm *drm = nouveau_drm(dev); in NVSetOwner()
96 NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX); in NVSetOwner()
97 NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX); in NVSetOwner()
101 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner); in NVSetOwner()
104 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); in NVSetOwner()
105 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); in NVSetOwner()
110 NVBlankScreen(struct drm_device *dev, int head, bool blank) in NVBlankScreen() argument
114 if (nv_two_heads(dev)) in NVBlankScreen()
115 NVSetOwner(dev, head); in NVBlankScreen()
117 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); in NVBlankScreen()
119 NVVgaSeqReset(dev, head, true); in NVBlankScreen()
121 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); in NVBlankScreen()
123 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); in NVBlankScreen()
124 NVVgaSeqReset(dev, head, false); in NVBlankScreen()
132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
135 struct nouveau_drm *drm = nouveau_drm(dev); in nouveau_hw_decode_pll()
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
164 nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype, in nouveau_hw_get_pllvals() argument
167 struct nouveau_drm *drm = nouveau_drm(dev); in nouveau_hw_get_pllvals()
181 else if (nv_two_reg_pll(dev)) { in nouveau_hw_get_pllvals()
188 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580); in nouveau_hw_get_pllvals()
199 nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals); in nouveau_hw_get_pllvals()
215 nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype) in nouveau_hw_get_clock() argument
217 struct pci_dev *pdev = to_pci_dev(dev->dev); in nouveau_hw_get_clock()
244 ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals); in nouveau_hw_get_clock()
252 nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head) in nouveau_hw_fix_bad_vpll() argument
260 struct nouveau_drm *drm = nouveau_drm(dev); in nouveau_hw_fix_bad_vpll()
270 nouveau_hw_get_pllvals(dev, pll, &pv); in nouveau_hw_fix_bad_vpll()
290 static void nouveau_vga_font_io(struct drm_device *dev, in nouveau_vga_font_io() argument
296 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane); in nouveau_vga_font_io()
297 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane); in nouveau_vga_font_io()
300 nv04_display(dev)->saved_vga_font[plane][i] = in nouveau_vga_font_io()
303 iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i], in nouveau_vga_font_io()
310 nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save) in nouveau_hw_save_vga_fonts() argument
312 struct nouveau_drm *drm = nouveau_drm(dev); in nouveau_hw_save_vga_fonts()
313 struct pci_dev *pdev = to_pci_dev(dev->dev); in nouveau_hw_save_vga_fonts()
319 if (nv_two_heads(dev)) in nouveau_hw_save_vga_fonts()
320 NVSetOwner(dev, 0); in nouveau_hw_save_vga_fonts()
322 NVSetEnablePalette(dev, 0, true); in nouveau_hw_save_vga_fonts()
323 graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1; in nouveau_hw_save_vga_fonts()
324 NVSetEnablePalette(dev, 0, false); in nouveau_hw_save_vga_fonts()
339 if (nv_two_heads(dev)) in nouveau_hw_save_vga_fonts()
340 NVBlankScreen(dev, 1, true); in nouveau_hw_save_vga_fonts()
341 NVBlankScreen(dev, 0, true); in nouveau_hw_save_vga_fonts()
344 misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ); in nouveau_hw_save_vga_fonts()
345 seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX); in nouveau_hw_save_vga_fonts()
346 seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX); in nouveau_hw_save_vga_fonts()
347 gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX); in nouveau_hw_save_vga_fonts()
348 gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX); in nouveau_hw_save_vga_fonts()
349 gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX); in nouveau_hw_save_vga_fonts()
351 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67); in nouveau_hw_save_vga_fonts()
352 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6); in nouveau_hw_save_vga_fonts()
353 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0); in nouveau_hw_save_vga_fonts()
354 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5); in nouveau_hw_save_vga_fonts()
358 nouveau_vga_font_io(dev, iovram, save, plane); in nouveau_hw_save_vga_fonts()
361 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc); in nouveau_hw_save_vga_fonts()
362 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4); in nouveau_hw_save_vga_fonts()
363 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5); in nouveau_hw_save_vga_fonts()
364 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6); in nouveau_hw_save_vga_fonts()
365 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2); in nouveau_hw_save_vga_fonts()
366 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4); in nouveau_hw_save_vga_fonts()
368 if (nv_two_heads(dev)) in nouveau_hw_save_vga_fonts()
369 NVBlankScreen(dev, 1, false); in nouveau_hw_save_vga_fonts()
370 NVBlankScreen(dev, 0, false); in nouveau_hw_save_vga_fonts()
380 rd_cio_state(struct drm_device *dev, int head, in rd_cio_state() argument
383 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index); in rd_cio_state()
387 wr_cio_state(struct drm_device *dev, int head, in wr_cio_state() argument
390 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); in wr_cio_state()
394 nv_save_state_ramdac(struct drm_device *dev, int head, in nv_save_state_ramdac() argument
397 struct nouveau_drm *drm = nouveau_drm(dev); in nv_save_state_ramdac()
402 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); in nv_save_state_ramdac()
404 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals); in nv_save_state_ramdac()
405 state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT); in nv_save_state_ramdac()
406 if (nv_two_heads(dev)) in nv_save_state_ramdac()
407 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); in nv_save_state_ramdac()
409 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); in nv_save_state_ramdac()
411 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); in nv_save_state_ramdac()
413 if (nv_gf4_disp_arch(dev)) in nv_save_state_ramdac()
414 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); in nv_save_state_ramdac()
416 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); in nv_save_state_ramdac()
418 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); in nv_save_state_ramdac()
419 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL); in nv_save_state_ramdac()
420 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW); in nv_save_state_ramdac()
421 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY); in nv_save_state_ramdac()
422 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL); in nv_save_state_ramdac()
423 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW); in nv_save_state_ramdac()
424 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY); in nv_save_state_ramdac()
425 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2); in nv_save_state_ramdac()
429 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); in nv_save_state_ramdac()
430 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20); in nv_save_state_ramdac()
433 if (nv_gf4_disp_arch(dev)) { in nv_save_state_ramdac()
434 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER); in nv_save_state_ramdac()
436 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4); in nv_save_state_ramdac()
437 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4); in nv_save_state_ramdac()
441 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); in nv_save_state_ramdac()
442 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0); in nv_save_state_ramdac()
443 if (!nv_gf4_disp_arch(dev) && head == 0) { in nv_save_state_ramdac()
446 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 & in nv_save_state_ramdac()
449 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1); in nv_save_state_ramdac()
450 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2); in nv_save_state_ramdac()
452 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR); in nv_save_state_ramdac()
454 if (nv_gf4_disp_arch(dev)) in nv_save_state_ramdac()
455 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); in nv_save_state_ramdac()
458 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); in nv_save_state_ramdac()
459 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); in nv_save_state_ramdac()
460 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); in nv_save_state_ramdac()
463 regp->ctv_regs[i] = NVReadRAMDAC(dev, head, in nv_save_state_ramdac()
469 nv_load_state_ramdac(struct drm_device *dev, int head, in nv_load_state_ramdac() argument
472 struct nouveau_drm *drm = nouveau_drm(dev); in nv_load_state_ramdac()
479 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); in nv_load_state_ramdac()
482 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel); in nv_load_state_ramdac()
483 if (nv_two_heads(dev)) in nv_load_state_ramdac()
484 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk); in nv_load_state_ramdac()
486 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); in nv_load_state_ramdac()
488 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); in nv_load_state_ramdac()
490 if (nv_gf4_disp_arch(dev)) in nv_load_state_ramdac()
491 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); in nv_load_state_ramdac()
493 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); in nv_load_state_ramdac()
495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); in nv_load_state_ramdac()
496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal); in nv_load_state_ramdac()
497 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew); in nv_load_state_ramdac()
498 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay); in nv_load_state_ramdac()
499 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal); in nv_load_state_ramdac()
500 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew); in nv_load_state_ramdac()
501 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay); in nv_load_state_ramdac()
502 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2); in nv_load_state_ramdac()
507 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); in nv_load_state_ramdac()
508 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]); in nv_load_state_ramdac()
511 if (nv_gf4_disp_arch(dev)) { in nv_load_state_ramdac()
512 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither); in nv_load_state_ramdac()
514 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]); in nv_load_state_ramdac()
515 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]); in nv_load_state_ramdac()
519 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control); in nv_load_state_ramdac()
520 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0); in nv_load_state_ramdac()
521 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1); in nv_load_state_ramdac()
522 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2); in nv_load_state_ramdac()
524 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color); in nv_load_state_ramdac()
526 if (nv_gf4_disp_arch(dev)) in nv_load_state_ramdac()
527 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); in nv_load_state_ramdac()
530 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); in nv_load_state_ramdac()
531 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); in nv_load_state_ramdac()
532 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); in nv_load_state_ramdac()
535 NVWriteRAMDAC(dev, head, in nv_load_state_ramdac()
541 nv_save_state_vga(struct drm_device *dev, int head, in nv_save_state_vga() argument
547 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ); in nv_save_state_vga()
550 rd_cio_state(dev, head, regp, i); in nv_save_state_vga()
552 NVSetEnablePalette(dev, head, true); in nv_save_state_vga()
554 regp->Attribute[i] = NVReadVgaAttr(dev, head, i); in nv_save_state_vga()
555 NVSetEnablePalette(dev, head, false); in nv_save_state_vga()
558 regp->Graphics[i] = NVReadVgaGr(dev, head, i); in nv_save_state_vga()
561 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i); in nv_save_state_vga()
565 nv_load_state_vga(struct drm_device *dev, int head, in nv_load_state_vga() argument
571 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg); in nv_load_state_vga()
574 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]); in nv_load_state_vga()
576 nv_lock_vga_crtc_base(dev, head, false); in nv_load_state_vga()
578 wr_cio_state(dev, head, regp, i); in nv_load_state_vga()
579 nv_lock_vga_crtc_base(dev, head, true); in nv_load_state_vga()
582 NVWriteVgaGr(dev, head, i, regp->Graphics[i]); in nv_load_state_vga()
584 NVSetEnablePalette(dev, head, true); in nv_load_state_vga()
586 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]); in nv_load_state_vga()
587 NVSetEnablePalette(dev, head, false); in nv_load_state_vga()
591 nv_save_state_ext(struct drm_device *dev, int head, in nv_save_state_ext() argument
594 struct nouveau_drm *drm = nouveau_drm(dev); in nv_save_state_ext()
598 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); in nv_save_state_ext()
599 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); in nv_save_state_ext()
600 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); in nv_save_state_ext()
601 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); in nv_save_state_ext()
602 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); in nv_save_state_ext()
603 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); in nv_save_state_ext()
604 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); in nv_save_state_ext()
606 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); in nv_save_state_ext()
607 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); in nv_save_state_ext()
608 rd_cio_state(dev, head, regp, NV_CIO_CRE_21); in nv_save_state_ext()
611 rd_cio_state(dev, head, regp, NV_CIO_CRE_47); in nv_save_state_ext()
614 rd_cio_state(dev, head, regp, 0x9f); in nv_save_state_ext()
616 rd_cio_state(dev, head, regp, NV_CIO_CRE_49); in nv_save_state_ext()
617 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); in nv_save_state_ext()
618 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); in nv_save_state_ext()
619 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); in nv_save_state_ext()
620 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); in nv_save_state_ext()
623 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); in nv_save_state_ext()
624 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); in nv_save_state_ext()
627 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); in nv_save_state_ext()
630 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); in nv_save_state_ext()
632 if (nv_two_heads(dev)) in nv_save_state_ext()
633 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL); in nv_save_state_ext()
634 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG); in nv_save_state_ext()
637 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG); in nv_save_state_ext()
639 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); in nv_save_state_ext()
640 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); in nv_save_state_ext()
642 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); in nv_save_state_ext()
643 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB); in nv_save_state_ext()
644 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); in nv_save_state_ext()
645 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); in nv_save_state_ext()
648 if (nv_gf4_disp_arch(dev)) { in nv_save_state_ext()
649 rd_cio_state(dev, head, regp, NV_CIO_CRE_42); in nv_save_state_ext()
650 rd_cio_state(dev, head, regp, NV_CIO_CRE_53); in nv_save_state_ext()
651 rd_cio_state(dev, head, regp, NV_CIO_CRE_54); in nv_save_state_ext()
654 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i); in nv_save_state_ext()
655 rd_cio_state(dev, head, regp, NV_CIO_CRE_59); in nv_save_state_ext()
656 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B); in nv_save_state_ext()
658 rd_cio_state(dev, head, regp, NV_CIO_CRE_85); in nv_save_state_ext()
659 rd_cio_state(dev, head, regp, NV_CIO_CRE_86); in nv_save_state_ext()
662 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START); in nv_save_state_ext()
666 nv_load_state_ext(struct drm_device *dev, int head, in nv_load_state_ext() argument
669 struct nouveau_drm *drm = nouveau_drm(dev); in nv_load_state_ext()
676 if (nv_two_heads(dev)) in nv_load_state_ext()
681 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl); in nv_load_state_ext()
693 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); in nv_load_state_ext()
694 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); in nv_load_state_ext()
695 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); in nv_load_state_ext()
698 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); in nv_load_state_ext()
701 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); in nv_load_state_ext()
703 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900); in nv_load_state_ext()
705 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000); in nv_load_state_ext()
707 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000); in nv_load_state_ext()
711 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg); in nv_load_state_ext()
713 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); in nv_load_state_ext()
714 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); in nv_load_state_ext()
715 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); in nv_load_state_ext()
716 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); in nv_load_state_ext()
717 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); in nv_load_state_ext()
718 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); in nv_load_state_ext()
719 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); in nv_load_state_ext()
720 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); in nv_load_state_ext()
721 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); in nv_load_state_ext()
724 wr_cio_state(dev, head, regp, NV_CIO_CRE_47); in nv_load_state_ext()
727 wr_cio_state(dev, head, regp, 0x9f); in nv_load_state_ext()
729 wr_cio_state(dev, head, regp, NV_CIO_CRE_49); in nv_load_state_ext()
730 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); in nv_load_state_ext()
731 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); in nv_load_state_ext()
732 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); in nv_load_state_ext()
734 nv_fix_nv40_hw_cursor(dev, head); in nv_load_state_ext()
735 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); in nv_load_state_ext()
737 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); in nv_load_state_ext()
738 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); in nv_load_state_ext()
740 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); in nv_load_state_ext()
741 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB); in nv_load_state_ext()
742 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); in nv_load_state_ext()
743 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); in nv_load_state_ext()
746 if (nv_gf4_disp_arch(dev)) { in nv_load_state_ext()
760 wr_cio_state(dev, head, regp, NV_CIO_CRE_42); in nv_load_state_ext()
761 wr_cio_state(dev, head, regp, NV_CIO_CRE_53); in nv_load_state_ext()
762 wr_cio_state(dev, head, regp, NV_CIO_CRE_54); in nv_load_state_ext()
765 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); in nv_load_state_ext()
766 wr_cio_state(dev, head, regp, NV_CIO_CRE_59); in nv_load_state_ext()
767 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B); in nv_load_state_ext()
769 wr_cio_state(dev, head, regp, NV_CIO_CRE_85); in nv_load_state_ext()
770 wr_cio_state(dev, head, regp, NV_CIO_CRE_86); in nv_load_state_ext()
773 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start); in nv_load_state_ext()
777 nv_save_state_palette(struct drm_device *dev, int head, in nv_save_state_palette() argument
780 struct nvif_object *device = &nouveau_drm(dev)->client.device.object; in nv_save_state_palette()
792 NVSetEnablePalette(dev, head, false); in nv_save_state_palette()
796 nouveau_hw_load_state_palette(struct drm_device *dev, int head, in nouveau_hw_load_state_palette() argument
799 struct nvif_object *device = &nouveau_drm(dev)->client.device.object; in nouveau_hw_load_state_palette()
811 NVSetEnablePalette(dev, head, false); in nouveau_hw_load_state_palette()
814 void nouveau_hw_save_state(struct drm_device *dev, int head, in nouveau_hw_save_state() argument
817 struct nouveau_drm *drm = nouveau_drm(dev); in nouveau_hw_save_state()
821 nouveau_hw_fix_bad_vpll(dev, head); in nouveau_hw_save_state()
822 nv_save_state_ramdac(dev, head, state); in nouveau_hw_save_state()
823 nv_save_state_vga(dev, head, state); in nouveau_hw_save_state()
824 nv_save_state_palette(dev, head, state); in nouveau_hw_save_state()
825 nv_save_state_ext(dev, head, state); in nouveau_hw_save_state()
828 void nouveau_hw_load_state(struct drm_device *dev, int head, in nouveau_hw_load_state() argument
831 NVVgaProtect(dev, head, true); in nouveau_hw_load_state()
832 nv_load_state_ramdac(dev, head, state); in nouveau_hw_load_state()
833 nv_load_state_ext(dev, head, state); in nouveau_hw_load_state()
834 nouveau_hw_load_state_palette(dev, head, state); in nouveau_hw_load_state()
835 nv_load_state_vga(dev, head, state); in nouveau_hw_load_state()
836 NVVgaProtect(dev, head, false); in nouveau_hw_load_state()