Lines Matching full:crtc
53 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
57 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) in crtc_wr_cio_state() argument
59 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, in crtc_wr_cio_state()
60 crtcstate->CRTC[index]); in crtc_wr_cio_state()
63 static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level) in nv_crtc_set_digital_vibrance() argument
65 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_set_digital_vibrance()
66 struct drm_device *dev = crtc->dev; in nv_crtc_set_digital_vibrance()
69 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; in nv_crtc_set_digital_vibrance()
70 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { in nv_crtc_set_digital_vibrance()
71 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; in nv_crtc_set_digital_vibrance()
72 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; in nv_crtc_set_digital_vibrance()
73 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); in nv_crtc_set_digital_vibrance()
75 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); in nv_crtc_set_digital_vibrance()
78 static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level) in nv_crtc_set_image_sharpening() argument
80 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_set_image_sharpening()
81 struct drm_device *dev = crtc->dev; in nv_crtc_set_image_sharpening()
88 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); in nv_crtc_set_image_sharpening()
117 static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_c… in nv_crtc_calc_state_ext() argument
119 struct drm_device *dev = crtc->dev; in nv_crtc_calc_state_ext()
123 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_calc_state_ext()
175 nv_crtc_dpms(struct drm_crtc *crtc, int mode) in nv_crtc_dpms() argument
177 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_dpms()
178 struct drm_device *dev = crtc->dev; in nv_crtc_dpms()
183 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode, in nv_crtc_dpms()
237 nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) in nv_crtc_mode_set_vga() argument
239 struct drm_device *dev = crtc->dev; in nv_crtc_mode_set_vga()
240 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_mode_set_vga()
242 struct drm_framebuffer *fb = crtc->primary->fb; in nv_crtc_mode_set_vga()
264 if (encoder->crtc == crtc && in nv_crtc_mode_set_vga()
343 * CRTC in nv_crtc_mode_set_vga()
345 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; in nv_crtc_mode_set_vga()
346 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; in nv_crtc_mode_set_vga()
347 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; in nv_crtc_mode_set_vga()
348 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | in nv_crtc_mode_set_vga()
350 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; in nv_crtc_mode_set_vga()
351 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | in nv_crtc_mode_set_vga()
353 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; in nv_crtc_mode_set_vga()
354 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | in nv_crtc_mode_set_vga()
362 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; in nv_crtc_mode_set_vga()
363 …regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL… in nv_crtc_mode_set_vga()
366 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; in nv_crtc_mode_set_vga()
367 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; in nv_crtc_mode_set_vga()
368 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; in nv_crtc_mode_set_vga()
369 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; in nv_crtc_mode_set_vga()
370 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; in nv_crtc_mode_set_vga()
371 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; in nv_crtc_mode_set_vga()
372 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; in nv_crtc_mode_set_vga()
373 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); in nv_crtc_mode_set_vga()
374 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; in nv_crtc_mode_set_vga()
375 /* framebuffer can be larger than crtc scanout area. */ in nv_crtc_mode_set_vga()
376 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8; in nv_crtc_mode_set_vga()
377 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; in nv_crtc_mode_set_vga()
378 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; in nv_crtc_mode_set_vga()
379 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; in nv_crtc_mode_set_vga()
380 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; in nv_crtc_mode_set_vga()
381 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; in nv_crtc_mode_set_vga()
384 * Some extended CRTC registers (they are not saved with the rest of the vga regs). in nv_crtc_mode_set_vga()
387 /* framebuffer can be larger than crtc scanout area. */ in nv_crtc_mode_set_vga()
388 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = in nv_crtc_mode_set_vga()
390 regp->CRTC[NV_CIO_CRE_42] = in nv_crtc_mode_set_vga()
392 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? in nv_crtc_mode_set_vga()
394 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | in nv_crtc_mode_set_vga()
399 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | in nv_crtc_mode_set_vga()
403 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | in nv_crtc_mode_set_vga()
410 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; in nv_crtc_mode_set_vga()
411 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); in nv_crtc_mode_set_vga()
413 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ in nv_crtc_mode_set_vga()
455 * The clocks, CRTCs and outputs attached to this CRTC must be off.
461 nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) in nv_crtc_mode_set_regs() argument
463 struct drm_device *dev = crtc->dev; in nv_crtc_mode_set_regs()
465 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_mode_set_regs()
468 const struct drm_framebuffer *fb = crtc->primary->fb; in nv_crtc_mode_set_regs()
477 if (encoder->crtc != crtc) in nv_crtc_mode_set_regs()
494 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); in nv_crtc_mode_set_regs()
497 /* Except for rare conditions I2C is enabled on the primary crtc */ in nv_crtc_mode_set_regs()
501 /* Set overlay to desired crtc. */ in nv_crtc_mode_set_regs()
519 regp->CRTC[NV_CIO_CRE_53] = 0; in nv_crtc_mode_set_regs()
520 regp->CRTC[NV_CIO_CRE_54] = 0; in nv_crtc_mode_set_regs()
524 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; in nv_crtc_mode_set_regs()
526 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; in nv_crtc_mode_set_regs()
528 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; in nv_crtc_mode_set_regs()
532 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; in nv_crtc_mode_set_regs()
534 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); in nv_crtc_mode_set_regs()
542 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; in nv_crtc_mode_set_regs()
544 /* The blob seems to take the current value from crtc 0, add 4 to that in nv_crtc_mode_set_regs()
545 * and reuse the old value for crtc 1 */ in nv_crtc_mode_set_regs()
546 …regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TV… in nv_crtc_mode_set_regs()
548 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; in nv_crtc_mode_set_regs()
552 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; in nv_crtc_mode_set_regs()
555 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; in nv_crtc_mode_set_regs()
574 regp->CRTC[NV_CIO_CRE_85] = 0xFF; in nv_crtc_mode_set_regs()
575 regp->CRTC[NV_CIO_CRE_86] = 0x1; in nv_crtc_mode_set_regs()
578 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8; in nv_crtc_mode_set_regs()
581 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); in nv_crtc_mode_set_regs()
600 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); in nv_crtc_mode_set_regs()
610 nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) in nv_crtc_swap_fbs() argument
612 struct nv04_display *disp = nv04_display(crtc->dev); in nv_crtc_swap_fbs()
613 struct drm_framebuffer *fb = crtc->primary->fb; in nv_crtc_swap_fbs()
615 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_swap_fbs()
631 * The clocks, CRTCs and outputs attached to this CRTC must be off.
637 nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, in nv_crtc_mode_set() argument
641 struct drm_device *dev = crtc->dev; in nv_crtc_mode_set()
642 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_mode_set()
646 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index); in nv_crtc_mode_set()
649 ret = nv_crtc_swap_fbs(crtc, old_fb); in nv_crtc_mode_set()
656 nv_crtc_mode_set_vga(crtc, adjusted_mode); in nv_crtc_mode_set()
660 nv_crtc_mode_set_regs(crtc, adjusted_mode); in nv_crtc_mode_set()
661 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); in nv_crtc_mode_set()
665 static void nv_crtc_save(struct drm_crtc *crtc) in nv_crtc_save() argument
667 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_save()
668 struct drm_device *dev = crtc->dev; in nv_crtc_save()
674 if (nv_two_heads(crtc->dev)) in nv_crtc_save()
675 NVSetOwner(crtc->dev, nv_crtc->index); in nv_crtc_save()
677 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); in nv_crtc_save()
681 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; in nv_crtc_save()
686 static void nv_crtc_restore(struct drm_crtc *crtc) in nv_crtc_restore() argument
688 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_restore()
689 struct drm_device *dev = crtc->dev; in nv_crtc_restore()
691 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; in nv_crtc_restore()
693 if (nv_two_heads(crtc->dev)) in nv_crtc_restore()
694 NVSetOwner(crtc->dev, head); in nv_crtc_restore()
696 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg); in nv_crtc_restore()
697 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21); in nv_crtc_restore()
702 static void nv_crtc_prepare(struct drm_crtc *crtc) in nv_crtc_prepare() argument
704 struct drm_device *dev = crtc->dev; in nv_crtc_prepare()
706 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_prepare()
707 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private; in nv_crtc_prepare()
712 drm_crtc_vblank_off(crtc); in nv_crtc_prepare()
713 funcs->dpms(crtc, DRM_MODE_DPMS_OFF); in nv_crtc_prepare()
725 static void nv_crtc_commit(struct drm_crtc *crtc) in nv_crtc_commit() argument
727 struct drm_device *dev = crtc->dev; in nv_crtc_commit()
728 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private; in nv_crtc_commit()
729 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_commit()
732 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL); in nv_crtc_commit()
743 funcs->dpms(crtc, DRM_MODE_DPMS_ON); in nv_crtc_commit()
744 drm_crtc_vblank_on(crtc); in nv_crtc_commit()
747 static void nv_crtc_destroy(struct drm_crtc *crtc) in nv_crtc_destroy() argument
749 struct nv04_display *disp = nv04_display(crtc->dev); in nv_crtc_destroy()
750 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_destroy()
755 drm_crtc_cleanup(crtc); in nv_crtc_destroy()
770 nv_crtc_gamma_load(struct drm_crtc *crtc) in nv_crtc_gamma_load() argument
772 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_gamma_load()
779 r = crtc->gamma_store; in nv_crtc_gamma_load()
780 g = r + crtc->gamma_size; in nv_crtc_gamma_load()
781 b = g + crtc->gamma_size; in nv_crtc_gamma_load()
793 nv_crtc_disable(struct drm_crtc *crtc) in nv_crtc_disable() argument
795 struct nv04_display *disp = nv04_display(crtc->dev); in nv_crtc_disable()
796 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_disable()
803 nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, in nv_crtc_gamma_set() argument
807 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_gamma_set()
819 nv_crtc_gamma_load(crtc); in nv_crtc_gamma_set()
825 nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, in nv04_crtc_do_mode_set_base() argument
829 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv04_crtc_do_mode_set_base()
830 struct drm_device *dev = crtc->dev; in nv04_crtc_do_mode_set_base()
840 if (!atomic && !crtc->primary->fb) { in nv04_crtc_do_mode_set_base()
851 drm_fb = crtc->primary->fb; in nv04_crtc_do_mode_set_base()
859 nv_crtc_gamma_load(crtc); in nv04_crtc_do_mode_set_base()
863 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; in nv04_crtc_do_mode_set_base()
864 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8; in nv04_crtc_do_mode_set_base()
868 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); in nv04_crtc_do_mode_set_base()
872 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; in nv04_crtc_do_mode_set_base()
873 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = in nv04_crtc_do_mode_set_base()
875 regp->CRTC[NV_CIO_CRE_42] = in nv04_crtc_do_mode_set_base()
877 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); in nv04_crtc_do_mode_set_base()
878 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); in nv04_crtc_do_mode_set_base()
879 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42); in nv04_crtc_do_mode_set_base()
887 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->format->cpp[0] * 8, in nv04_crtc_do_mode_set_base()
890 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; in nv04_crtc_do_mode_set_base()
891 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; in nv04_crtc_do_mode_set_base()
892 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); in nv04_crtc_do_mode_set_base()
893 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); in nv04_crtc_do_mode_set_base()
896 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; in nv04_crtc_do_mode_set_base()
897 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); in nv04_crtc_do_mode_set_base()
904 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, in nv04_crtc_mode_set_base() argument
907 int ret = nv_crtc_swap_fbs(crtc, old_fb); in nv04_crtc_mode_set_base()
910 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false); in nv04_crtc_mode_set_base()
914 nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc, in nv04_crtc_mode_set_base_atomic() argument
918 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true); in nv04_crtc_mode_set_base_atomic()
982 nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, in nv04_crtc_cursor_set() argument
985 struct nouveau_drm *drm = nouveau_drm(crtc->dev); in nv04_crtc_cursor_set()
987 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv04_crtc_cursor_set()
1024 nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) in nv04_crtc_cursor_move() argument
1026 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv04_crtc_cursor_move()
1035 struct drm_crtc *crtc; member
1060 drm_crtc_arm_vblank_event(s->crtc, s->event); in nv04_finish_page_flip()
1062 /* Give up ownership of vblank for page-flipped crtc */ in nv04_finish_page_flip()
1063 drm_crtc_vblank_put(s->crtc); in nv04_finish_page_flip()
1084 nv_set_crtc_base(drm->dev, drm_crtc_index(state.crtc), in nv04_flip_complete()
1085 state.offset + state.crtc->y * in nv04_flip_complete()
1086 state.pitch + state.crtc->x * in nv04_flip_complete()
1138 nv04_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, in nv04_crtc_page_flip() argument
1143 struct drm_device *dev = crtc->dev; in nv04_crtc_page_flip()
1145 struct drm_framebuffer *old_fb = crtc->primary->fb; in nv04_crtc_page_flip()
1154 int head = nouveau_crtc(crtc)->index; in nv04_crtc_page_flip()
1195 { { }, event, crtc, fb->format->cpp[0] * 8, fb->pitches[0], in nv04_crtc_page_flip()
1198 /* Keep vblanks on during flip, for the target crtc of this flip */ in nv04_crtc_page_flip()
1199 drm_crtc_vblank_get(crtc); in nv04_crtc_page_flip()
1220 /* Update the crtc struct and cleanup */ in nv04_crtc_page_flip()
1221 crtc->primary->fb = fb; in nv04_crtc_page_flip()
1231 drm_crtc_vblank_put(crtc); in nv04_crtc_page_flip()