2  * SPDX-License-Identifier: GPL-2.0
31 #define DEFAULT_REG_BW	153600 /* Used in mdss fbdev driver */
57 	path0 = devm_of_icc_get(dev, "mdp0-mem");  in msm_mdss_parse_data_bus_icc_path()
61 	msm_mdss->mdp_path[0] = path0;  in msm_mdss_parse_data_bus_icc_path()
62 	msm_mdss->num_mdp_paths = 1;  in msm_mdss_parse_data_bus_icc_path()
64 	path1 = devm_of_icc_get(dev, "mdp1-mem");  in msm_mdss_parse_data_bus_icc_path()
66 		msm_mdss->mdp_path[1] = path1;  in msm_mdss_parse_data_bus_icc_path()
67 		msm_mdss->num_mdp_paths++;  in msm_mdss_parse_data_bus_icc_path()
70 	reg_bus_path = of_icc_get(dev, "cpu-cfg");  in msm_mdss_parse_data_bus_icc_path()
72 		msm_mdss->reg_bus_path = reg_bus_path;  in msm_mdss_parse_data_bus_icc_path()
81 	for (i = 0; i < msm_mdss->num_mdp_paths; i++)  in msm_mdss_icc_request_bw()
82 		icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw));  in msm_mdss_icc_request_bw()
93 	interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS);  in msm_mdss_irq()
96 		irq_hw_number_t hwirq = fls(interrupts) - 1;  in msm_mdss_irq()
99 		rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain,  in msm_mdss_irq()
102 			dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n",  in msm_mdss_irq()
119 	clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);  in msm_mdss_irq_mask()
130 	set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);  in msm_mdss_irq_unmask()
146 	struct msm_mdss *msm_mdss = domain->host_data;  in msm_mdss_irqdomain_map()
164 	dev = msm_mdss->dev;  in _msm_mdss_irq_domain_add()
166 	domain = irq_domain_add_linear(dev->of_node, 32,  in _msm_mdss_irq_domain_add()
170 		return -EINVAL;  in _msm_mdss_irq_domain_add()
173 	msm_mdss->irq_controller.enabled_mask = 0;  in _msm_mdss_irq_domain_add()
174 	msm_mdss->irq_controller.domain = domain;  in _msm_mdss_irq_domain_add()
181 	const struct msm_mdss_data *data = msm_mdss->mdss_data;  in msm_mdss_setup_ubwc_dec_20()
183 	writel_relaxed(data->ubwc_static, msm_mdss->mmio + UBWC_STATIC);  in msm_mdss_setup_ubwc_dec_20()
188 	const struct msm_mdss_data *data = msm_mdss->mdss_data;  in msm_mdss_setup_ubwc_dec_30()
189 	u32 value = (data->ubwc_swizzle & 0x1) |  in msm_mdss_setup_ubwc_dec_30()
190 		    (data->highest_bank_bit & 0x3) << 4 |  in msm_mdss_setup_ubwc_dec_30()
191 		    (data->macrotile_mode & 0x1) << 12;  in msm_mdss_setup_ubwc_dec_30()
193 	if (data->ubwc_enc_version == UBWC_3_0)  in msm_mdss_setup_ubwc_dec_30()
196 	if (data->ubwc_enc_version == UBWC_1_0)  in msm_mdss_setup_ubwc_dec_30()
199 	writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);  in msm_mdss_setup_ubwc_dec_30()
204 	const struct msm_mdss_data *data = msm_mdss->mdss_data;  in msm_mdss_setup_ubwc_dec_40()
205 	u32 value = (data->ubwc_swizzle & 0x7) |  in msm_mdss_setup_ubwc_dec_40()
206 		    (data->ubwc_static & 0x1) << 3 |  in msm_mdss_setup_ubwc_dec_40()
207 		    (data->highest_bank_bit & 0x7) << 4 |  in msm_mdss_setup_ubwc_dec_40()
208 		    (data->macrotile_mode & 0x1) << 12;  in msm_mdss_setup_ubwc_dec_40()
210 	writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);  in msm_mdss_setup_ubwc_dec_40()
212 	if (data->ubwc_enc_version == UBWC_3_0) {  in msm_mdss_setup_ubwc_dec_40()
213 		writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2);  in msm_mdss_setup_ubwc_dec_40()
214 		writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE);  in msm_mdss_setup_ubwc_dec_40()
216 		if (data->ubwc_dec_version == UBWC_4_3)  in msm_mdss_setup_ubwc_dec_40()
217 			writel_relaxed(3, msm_mdss->mmio + UBWC_CTRL_2);  in msm_mdss_setup_ubwc_dec_40()
219 			writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);  in msm_mdss_setup_ubwc_dec_40()
220 		writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE);  in msm_mdss_setup_ubwc_dec_40()
226 	struct msm_mdss *mdss;  in msm_mdss_get_mdss_data()  local
229 		return ERR_PTR(-EINVAL);  in msm_mdss_get_mdss_data()
231 	mdss = dev_get_drvdata(dev);  in msm_mdss_get_mdss_data()
233 	return mdss->mdss_data;  in msm_mdss_get_mdss_data()
242 	 * the interconnect is enabled (non-zero bandwidth). Let's make sure  in msm_mdss_enable()
247 	if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw)  in msm_mdss_enable()
248 		icc_set_bw(msm_mdss->reg_bus_path, 0,  in msm_mdss_enable()
249 			   msm_mdss->mdss_data->reg_bus_bw);  in msm_mdss_enable()
251 		icc_set_bw(msm_mdss->reg_bus_path, 0,  in msm_mdss_enable()
254 	ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);  in msm_mdss_enable()
256 		dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret);  in msm_mdss_enable()
262 	 * mdss on mdp5 hardware. Skip it for now.  in msm_mdss_enable()
264 	if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data)  in msm_mdss_enable()
268 	 * ubwc config is part of the "mdss" region which is not accessible  in msm_mdss_enable()
274 	switch (msm_mdss->mdss_data->ubwc_dec_version) {  in msm_mdss_enable()
290 		dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n",  in msm_mdss_enable()
291 			msm_mdss->mdss_data->ubwc_dec_version);  in msm_mdss_enable()
292 		dev_err(msm_mdss->dev, "HW_REV: 0x%x\n",  in msm_mdss_enable()
293 			readl_relaxed(msm_mdss->mmio + HW_REV));  in msm_mdss_enable()
294 		dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n",  in msm_mdss_enable()
295 			readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION));  in msm_mdss_enable()
304 	clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks);  in msm_mdss_disable()
307 	if (msm_mdss->reg_bus_path)  in msm_mdss_disable()
308 		icc_set_bw(msm_mdss->reg_bus_path, 0, 0);  in msm_mdss_disable()
315 	struct platform_device *pdev = to_platform_device(msm_mdss->dev);  in msm_mdss_destroy()
318 	pm_runtime_suspend(msm_mdss->dev);  in msm_mdss_destroy()
319 	pm_runtime_disable(msm_mdss->dev);  in msm_mdss_destroy()
320 	irq_domain_remove(msm_mdss->irq_controller.domain);  in msm_mdss_destroy()
321 	msm_mdss->irq_controller.domain = NULL;  in msm_mdss_destroy()
336 				     "failed to acquire mdss reset\n");  in msm_mdss_reset()
353  * MDP5 MDSS uses at most three specified clocks.
363 		return -EINVAL;  in mdp5_mdss_parse_clock()
365 	bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL);  in mdp5_mdss_parse_clock()
367 		return -ENOMEM;  in mdp5_mdss_parse_clock()
373 	ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk);  in mdp5_mdss_parse_clock()
388 	ret = msm_mdss_reset(&pdev->dev);  in msm_mdss_init()
392 	msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL);  in msm_mdss_init()
394 		return ERR_PTR(-ENOMEM);  in msm_mdss_init()
396 	msm_mdss->mdss_data = of_device_get_match_data(&pdev->dev);  in msm_mdss_init()
398 	msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");  in msm_mdss_init()
399 	if (IS_ERR(msm_mdss->mmio))  in msm_mdss_init()
400 		return ERR_CAST(msm_mdss->mmio);  in msm_mdss_init()
402 	dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio);  in msm_mdss_init()
404 	ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss);  in msm_mdss_init()
409 		ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks);  in msm_mdss_init()
411 		ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks);  in msm_mdss_init()
413 		dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret);  in msm_mdss_init()
416 	msm_mdss->num_clocks = ret;  in msm_mdss_init()
417 	msm_mdss->is_mdp5 = is_mdp5;  in msm_mdss_init()
419 	msm_mdss->dev = &pdev->dev;  in msm_mdss_init()
432 	pm_runtime_enable(&pdev->dev);  in msm_mdss_init()
439 	struct msm_mdss *mdss = dev_get_drvdata(dev);  in mdss_runtime_suspend()  local
443 	return msm_mdss_disable(mdss);  in mdss_runtime_suspend()
448 	struct msm_mdss *mdss = dev_get_drvdata(dev);  in mdss_runtime_resume()  local
452 	return msm_mdss_enable(mdss);  in mdss_runtime_resume()
479 	struct msm_mdss *mdss;  in mdss_probe()  local
480 	bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss");  in mdss_probe()
481 	struct device *dev = &pdev->dev;  in mdss_probe()
484 	mdss = msm_mdss_init(pdev, is_mdp5);  in mdss_probe()
485 	if (IS_ERR(mdss))  in mdss_probe()
486 		return PTR_ERR(mdss);  in mdss_probe()
488 	platform_set_drvdata(pdev, mdss);  in mdss_probe()
492 	 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.  in mdss_probe()
496 	ret = of_platform_populate(dev->of_node, NULL, NULL, dev);  in mdss_probe()
499 		msm_mdss_destroy(mdss);  in mdss_probe()
508 	struct msm_mdss *mdss = platform_get_drvdata(pdev);  in mdss_remove()  local
510 	of_platform_depopulate(&pdev->dev);  in mdss_remove()
512 	msm_mdss_destroy(mdss);  in mdss_remove()
639 	{ .compatible = "qcom,mdss" },
640 	{ .compatible = "qcom,msm8998-mdss", .data = &msm8998_data },
641 	{ .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data },
642 	{ .compatible = "qcom,sdm845-mdss", .data = &sdm845_data },
643 	{ .compatible = "qcom,sc7180-mdss", .data = &sc7180_data },
644 	{ .compatible = "qcom,sc7280-mdss", .data = &sc7280_data },
645 	{ .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
646 	{ .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
647 	{ .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
648 	{ .compatible = "qcom,sm6125-mdss", .data = &sm6125_data },
649 	{ .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
650 	{ .compatible = "qcom,sm6375-mdss", .data = &sm6350_data },
651 	{ .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
652 	{ .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
653 	{ .compatible = "qcom,sm8350-mdss", .data = &sm8350_data },
654 	{ .compatible = "qcom,sm8450-mdss", .data = &sm8350_data },
655 	{ .compatible = "qcom,sm8550-mdss", .data = &sm8550_data },
664 		.name   = "msm-mdss",