259 	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);  in dsi_pll_10nm_vco_set_rate()  local
262 	DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->phy->id, rate,  in dsi_pll_10nm_vco_set_rate()
265 	pll_10nm->vco_current_rate = rate;  in dsi_pll_10nm_vco_set_rate()
269 	dsi_pll_calc_dec_frac(pll_10nm, &config);  in dsi_pll_10nm_vco_set_rate()
271 	dsi_pll_calc_ssc(pll_10nm, &config);  in dsi_pll_10nm_vco_set_rate()
273 	dsi_pll_commit(pll_10nm, &config);  in dsi_pll_10nm_vco_set_rate()
275 	dsi_pll_config_hzindep_reg(pll_10nm);  in dsi_pll_10nm_vco_set_rate()
277 	dsi_pll_ssc_commit(pll_10nm, &config);  in dsi_pll_10nm_vco_set_rate()
346 	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);  in dsi_pll_10nm_vco_prepare()  local
347 	struct device *dev = &pll_10nm->phy->pdev->dev;  in dsi_pll_10nm_vco_prepare()
350 	dsi_pll_enable_pll_bias(pll_10nm);  in dsi_pll_10nm_vco_prepare()
351 	if (pll_10nm->slave)  in dsi_pll_10nm_vco_prepare()
352 		dsi_pll_enable_pll_bias(pll_10nm->slave);  in dsi_pll_10nm_vco_prepare()
354 	rc = dsi_pll_10nm_vco_set_rate(hw,pll_10nm->vco_current_rate, 0);  in dsi_pll_10nm_vco_prepare()
361 	dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,  in dsi_pll_10nm_vco_prepare()
371 	rc = dsi_pll_10nm_lock_status(pll_10nm);  in dsi_pll_10nm_vco_prepare()
373 		DRM_DEV_ERROR(dev, "PLL(%d) lock failed\n", pll_10nm->phy->id);  in dsi_pll_10nm_vco_prepare()
377 	pll_10nm->phy->pll_on = true;  in dsi_pll_10nm_vco_prepare()
379 	dsi_pll_enable_global_clk(pll_10nm);  in dsi_pll_10nm_vco_prepare()
380 	if (pll_10nm->slave)  in dsi_pll_10nm_vco_prepare()
381 		dsi_pll_enable_global_clk(pll_10nm->slave);  in dsi_pll_10nm_vco_prepare()
383 	dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL,  in dsi_pll_10nm_vco_prepare()
385 	if (pll_10nm->slave)  in dsi_pll_10nm_vco_prepare()
386 		dsi_phy_write(pll_10nm->slave->phy->base +  in dsi_pll_10nm_vco_prepare()
401 	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);  in dsi_pll_10nm_vco_unprepare()  local
408 	dsi_pll_disable_global_clk(pll_10nm);  in dsi_pll_10nm_vco_unprepare()
409 	dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0);  in dsi_pll_10nm_vco_unprepare()
410 	dsi_pll_disable_sub(pll_10nm);  in dsi_pll_10nm_vco_unprepare()
411 	if (pll_10nm->slave) {  in dsi_pll_10nm_vco_unprepare()
412 		dsi_pll_disable_global_clk(pll_10nm->slave);  in dsi_pll_10nm_vco_unprepare()
413 		dsi_pll_disable_sub(pll_10nm->slave);  in dsi_pll_10nm_vco_unprepare()
417 	pll_10nm->phy->pll_on = false;  in dsi_pll_10nm_vco_unprepare()
423 	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);  in dsi_pll_10nm_vco_recalc_rate()  local
424 	void __iomem *base = pll_10nm->phy->pll_base;  in dsi_pll_10nm_vco_recalc_rate()
451 	pll_10nm->vco_current_rate = vco_rate;  in dsi_pll_10nm_vco_recalc_rate()
454 	    pll_10nm->phy->id, (unsigned long)vco_rate, dec, frac);  in dsi_pll_10nm_vco_recalc_rate()
462 	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);  in dsi_pll_10nm_clk_round_rate()  local
464 	if      (rate < pll_10nm->phy->cfg->min_pll_rate)  in dsi_pll_10nm_clk_round_rate()
465 		return  pll_10nm->phy->cfg->min_pll_rate;  in dsi_pll_10nm_clk_round_rate()
466 	else if (rate > pll_10nm->phy->cfg->max_pll_rate)  in dsi_pll_10nm_clk_round_rate()
467 		return  pll_10nm->phy->cfg->max_pll_rate;  in dsi_pll_10nm_clk_round_rate()
486 	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);  in dsi_10nm_pll_save_state()  local
487 	struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;  in dsi_10nm_pll_save_state()
488 	void __iomem *phy_base = pll_10nm->phy->base;  in dsi_10nm_pll_save_state()
491 	cached->pll_out_div = dsi_phy_read(pll_10nm->phy->pll_base +  in dsi_10nm_pll_save_state()
503 	    pll_10nm->phy->id, cached->pll_out_div, cached->bit_clk_div,  in dsi_10nm_pll_save_state()
509 	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);  in dsi_10nm_pll_restore_state()  local
510 	struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;  in dsi_10nm_pll_restore_state()
511 	void __iomem *phy_base = pll_10nm->phy->base;  in dsi_10nm_pll_restore_state()
515 	val = dsi_phy_read(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);  in dsi_10nm_pll_restore_state()
518 	dsi_phy_write(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val);  in dsi_10nm_pll_restore_state()
529 			pll_10nm->vco_current_rate,  in dsi_10nm_pll_restore_state()
532 		DRM_DEV_ERROR(&pll_10nm->phy->pdev->dev,  in dsi_10nm_pll_restore_state()
537 	DBG("DSI PLL%d", pll_10nm->phy->id);  in dsi_10nm_pll_restore_state()
544 	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);  in dsi_10nm_set_usecase()  local
548 	DBG("DSI PLL%d", pll_10nm->phy->id);  in dsi_10nm_set_usecase()
554 		pll_10nm->slave = pll_10nm_list[(pll_10nm->phy->id + 1) % DSI_MAX];  in dsi_10nm_set_usecase()
575 static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **provided_clocks)  in pll_10nm_register()  argument
587 	struct device *dev = &pll_10nm->phy->pdev->dev;  in pll_10nm_register()
592 	DBG("DSI%d", pll_10nm->phy->id);  in pll_10nm_register()
594 	snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_10nm->phy->id);  in pll_10nm_register()
595 	pll_10nm->clk_hw.init = &vco_init;  in pll_10nm_register()
597 	ret = devm_clk_hw_register(dev, &pll_10nm->clk_hw);  in pll_10nm_register()
601 	snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", pll_10nm->phy->id);  in pll_10nm_register()
604 			&pll_10nm->clk_hw, CLK_SET_RATE_PARENT,  in pll_10nm_register()
605 			pll_10nm->phy->pll_base +  in pll_10nm_register()
613 	snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", pll_10nm->phy->id);  in pll_10nm_register()
618 			pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,  in pll_10nm_register()
619 			0, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock);  in pll_10nm_register()
625 	snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_byteclk", pll_10nm->phy->id);  in pll_10nm_register()
637 	snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id);  in pll_10nm_register()
646 	snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id);  in pll_10nm_register()
655 	snprintf(clk_name, sizeof(clk_name), "dsi%d_pclk_mux", pll_10nm->phy->id);  in pll_10nm_register()
663 			}), 4, 0, pll_10nm->phy->base +  in pll_10nm_register()
670 	snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_dsiclk", pll_10nm->phy->id);  in pll_10nm_register()
674 			0, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,  in pll_10nm_register()
675 			4, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock);  in pll_10nm_register()
693 	struct dsi_pll_10nm *pll_10nm;  in dsi_pll_10nm_init()  local
696 	pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL);  in dsi_pll_10nm_init()
697 	if (!pll_10nm)  in dsi_pll_10nm_init()
702 	pll_10nm_list[phy->id] = pll_10nm;  in dsi_pll_10nm_init()
704 	spin_lock_init(&pll_10nm->postdiv_lock);  in dsi_pll_10nm_init()
706 	pll_10nm->phy = phy;  in dsi_pll_10nm_init()
708 	ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws);  in dsi_pll_10nm_init()
714 	phy->vco_hw = &pll_10nm->clk_hw;  in dsi_pll_10nm_init()