Lines Matching +full:0 +full:x00000064
56 #define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000
58 #define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004
60 #define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008
62 #define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c
64 #define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010
66 #define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014
68 #define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018
70 #define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c
72 #define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020
74 #define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024
76 #define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028
78 #define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c
80 #define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030
82 #define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034
84 #define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038
86 #define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c
88 #define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040
90 #define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0
92 #define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4
94 #define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8
96 #define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac
98 #define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0
100 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
102 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
104 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
106 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
108 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
110 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
112 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
114 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
116 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
118 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
120 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
122 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
124 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
126 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
128 #define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
130 #define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
132 #define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
134 #define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
136 #define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
138 #define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
140 #define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
142 #define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
144 #define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
146 #define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110
148 #define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114
150 #define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128
152 #define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140
154 #define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148
156 #define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c
158 #define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10 0x000001ac
160 static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_7nm_PHY_LN()
162 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_CFG0()
164 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_CFG1()
166 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_CFG2()
168 static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0;… in REG_DSI_7nm_PHY_LN_TEST_DATAPATH()
170 static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_PIN_SWAP()
172 static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_LPRX_CTRL()
174 static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } in REG_DSI_7nm_PHY_LN_TX_DCTRL()
176 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
178 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
180 #define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
182 #define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
184 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
186 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
188 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
190 #define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
192 #define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020
194 #define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
196 #define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028
198 #define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
200 #define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030
202 #define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034
204 #define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038
206 #define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
208 #define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040
210 #define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
212 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
214 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
216 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
218 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054
220 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058
222 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
224 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
226 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
228 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
230 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
232 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
234 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
236 #define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
238 #define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
240 #define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
242 #define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
244 #define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
246 #define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
248 #define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090
250 #define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094
252 #define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098
254 #define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c
256 #define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0
258 #define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4
260 #define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8
262 #define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
264 #define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
266 #define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
268 #define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
270 #define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
272 #define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0
274 #define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
276 #define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
278 #define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
280 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
282 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
284 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
286 #define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
288 #define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
290 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
292 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
294 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
296 #define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
298 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
300 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
302 #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
304 #define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100
306 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
308 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
310 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
312 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
314 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
316 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
318 #define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
320 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
322 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
324 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
326 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
328 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
330 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
332 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
334 #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
336 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
338 #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
340 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
342 #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
344 #define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150
346 #define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
348 #define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
350 #define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
352 #define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
354 #define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
356 #define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
358 #define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
360 #define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
362 #define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
364 #define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
366 #define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
368 #define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
370 #define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
372 #define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
374 #define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
376 #define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
378 #define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
380 #define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
382 #define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
384 #define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
386 #define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
388 #define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
390 #define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
392 #define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
394 #define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
396 #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
398 #define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
400 #define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
402 #define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4
404 #define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
406 #define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
408 #define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
410 #define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4
412 #define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
414 #define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc
416 #define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0
418 #define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4
420 #define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8
422 #define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec
424 #define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0
426 #define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4
428 #define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8
430 #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
432 #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200
434 #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204
436 #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208
438 #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c
440 #define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
442 #define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214
444 #define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
446 #define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
448 #define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220
450 #define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224
452 #define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
454 #define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
456 #define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
458 #define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
460 #define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
462 #define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
464 #define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240
466 #define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244
468 #define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
470 #define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
472 #define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250
474 #define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254
476 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
478 #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
480 #define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260