Lines Matching +full:0 +full:x00000064
56 #define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000
58 #define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004
60 #define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008
62 #define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c
64 #define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010
66 #define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014
68 #define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018
70 #define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c
72 #define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020
74 #define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024
76 #define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028
78 #define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c
80 #define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030
82 #define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034
84 #define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038
86 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098
88 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c
90 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0
92 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4
94 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8
96 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac
98 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0
100 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4
102 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8
104 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc
106 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0
108 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4
110 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8
112 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc
114 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0
116 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4
118 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8
120 #define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec
122 #define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4
124 #define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8
126 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_10nm_PHY_LN()
128 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG0()
130 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG1()
132 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG2()
134 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG3()
136 static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0… in REG_DSI_10nm_PHY_LN_TEST_DATAPATH()
138 static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_PIN_SWAP()
140 static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0… in REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL()
142 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*… in REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL()
144 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*… in REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL()
146 static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0… in REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL()
148 static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_LPRX_CTRL()
150 static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; } in REG_DSI_10nm_PHY_LN_TX_DCTRL()
152 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
154 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
156 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
158 #define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c
160 #define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020
162 #define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024
164 #define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c
166 #define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030
168 #define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054
170 #define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064
172 #define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c
174 #define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080
176 #define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094
178 #define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4
180 #define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8
182 #define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4
184 #define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc
186 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0
188 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4
190 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8
192 #define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c
194 #define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110
196 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114
198 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118
200 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c
202 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120
204 #define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c
206 #define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140
208 #define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144
210 #define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c
212 #define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154
214 #define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c
216 #define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164
218 #define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180
220 #define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184
222 #define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c
224 #define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0