Lines Matching +full:0 +full:x00000004
10 #define REG_DP_HW_VERSION (0x00000000)
12 #define REG_DP_SW_RESET (0x00000010)
13 #define DP_SW_RESET (0x00000001)
15 #define REG_DP_PHY_CTRL (0x00000014)
16 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001)
17 #define DP_PHY_CTRL_SW_RESET (0x00000004)
19 #define REG_DP_CLK_CTRL (0x00000018)
20 #define REG_DP_CLK_ACTIVE (0x0000001C)
21 #define REG_DP_INTR_STATUS (0x00000020)
22 #define REG_DP_INTR_STATUS2 (0x00000024)
23 #define REG_DP_INTR_STATUS3 (0x00000028)
25 #define REG_DP_INTR_STATUS4 (0x0000002C)
26 #define PSR_UPDATE_INT (0x00000001)
27 #define PSR_CAPTURE_INT (0x00000004)
28 #define PSR_EXIT_INT (0x00000010)
29 #define PSR_UPDATE_ERROR_INT (0x00000040)
30 #define PSR_WAKE_ERROR_INT (0x00000100)
32 #define REG_DP_INTR_MASK4 (0x00000030)
33 #define PSR_UPDATE_MASK (0x00000001)
34 #define PSR_CAPTURE_MASK (0x00000002)
35 #define PSR_EXIT_MASK (0x00000004)
36 #define PSR_UPDATE_ERROR_MASK (0x00000008)
37 #define PSR_WAKE_ERROR_MASK (0x00000010)
39 #define REG_DP_DP_HPD_CTRL (0x00000000)
40 #define DP_DP_HPD_CTRL_HPD_EN (0x00000001)
42 #define REG_DP_DP_HPD_INT_STATUS (0x00000004)
44 #define REG_DP_DP_HPD_INT_ACK (0x00000008)
45 #define DP_DP_HPD_PLUG_INT_ACK (0x00000001)
46 #define DP_DP_IRQ_HPD_INT_ACK (0x00000002)
47 #define DP_DP_HPD_REPLUG_INT_ACK (0x00000004)
48 #define DP_DP_HPD_UNPLUG_INT_ACK (0x00000008)
49 #define DP_DP_HPD_STATE_STATUS_BITS_MASK (0x0000000F)
50 #define DP_DP_HPD_STATE_STATUS_BITS_SHIFT (0x1C)
52 #define REG_DP_DP_HPD_INT_MASK (0x0000000C)
53 #define DP_DP_HPD_PLUG_INT_MASK (0x00000001)
54 #define DP_DP_IRQ_HPD_INT_MASK (0x00000002)
55 #define DP_DP_HPD_REPLUG_INT_MASK (0x00000004)
56 #define DP_DP_HPD_UNPLUG_INT_MASK (0x00000008)
61 #define DP_DP_HPD_STATE_STATUS_CONNECTED (0x40000000)
62 #define DP_DP_HPD_STATE_STATUS_PENDING (0x20000000)
63 #define DP_DP_HPD_STATE_STATUS_DISCONNECTED (0x00000000)
64 #define DP_DP_HPD_STATE_STATUS_MASK (0xE0000000)
66 #define REG_DP_DP_HPD_REFTIMER (0x00000018)
69 #define REG_DP_DP_HPD_EVENT_TIME_0 (0x0000001C)
70 #define REG_DP_DP_HPD_EVENT_TIME_1 (0x00000020)
71 #define DP_DP_HPD_EVENT_TIME_0_VAL (0x3E800FA)
72 #define DP_DP_HPD_EVENT_TIME_1_VAL (0x1F407D0)
74 #define REG_DP_AUX_CTRL (0x00000030)
75 #define DP_AUX_CTRL_ENABLE (0x00000001)
76 #define DP_AUX_CTRL_RESET (0x00000002)
78 #define REG_DP_AUX_DATA (0x00000034)
79 #define DP_AUX_DATA_READ (0x00000001)
80 #define DP_AUX_DATA_WRITE (0x00000000)
81 #define DP_AUX_DATA_OFFSET (0x00000008)
82 #define DP_AUX_DATA_INDEX_OFFSET (0x00000010)
83 #define DP_AUX_DATA_MASK (0x0000ff00)
84 #define DP_AUX_DATA_INDEX_WRITE (0x80000000)
86 #define REG_DP_AUX_TRANS_CTRL (0x00000038)
87 #define DP_AUX_TRANS_CTRL_I2C (0x00000100)
88 #define DP_AUX_TRANS_CTRL_GO (0x00000200)
89 #define DP_AUX_TRANS_CTRL_NO_SEND_ADDR (0x00000400)
90 #define DP_AUX_TRANS_CTRL_NO_SEND_STOP (0x00000800)
92 #define REG_DP_TIMEOUT_COUNT (0x0000003C)
93 #define REG_DP_AUX_LIMITS (0x00000040)
94 #define REG_DP_AUX_STATUS (0x00000044)
96 #define DP_DPCD_CP_IRQ (0x201)
97 #define DP_DPCD_RXSTATUS (0x69493)
99 #define DP_INTERRUPT_TRANS_NUM (0x000000A0)
101 #define REG_DP_MAINLINK_CTRL (0x00000000)
102 #define DP_MAINLINK_CTRL_ENABLE (0x00000001)
103 #define DP_MAINLINK_CTRL_RESET (0x00000002)
104 #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010)
105 #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000)
107 #define REG_DP_STATE_CTRL (0x00000004)
108 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN1 (0x00000001)
109 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN2 (0x00000002)
110 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN3 (0x00000004)
111 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN4 (0x00000008)
112 #define DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE (0x00000010)
113 #define DP_STATE_CTRL_LINK_PRBS7 (0x00000020)
114 #define DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN (0x00000040)
115 #define DP_STATE_CTRL_SEND_VIDEO (0x00000080)
116 #define DP_STATE_CTRL_PUSH_IDLE (0x00000100)
118 #define REG_DP_CONFIGURATION_CTRL (0x00000008)
119 #define DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK (0x00000001)
120 #define DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN (0x00000002)
121 #define DP_CONFIGURATION_CTRL_P_INTERLACED (0x00000004)
122 #define DP_CONFIGURATION_CTRL_INTERLACED_BTF (0x00000008)
123 #define DP_CONFIGURATION_CTRL_NUM_OF_LANES (0x00000010)
124 #define DP_CONFIGURATION_CTRL_ENHANCED_FRAMING (0x00000040)
125 #define DP_CONFIGURATION_CTRL_SEND_VSC (0x00000080)
126 #define DP_CONFIGURATION_CTRL_BPC (0x00000100)
127 #define DP_CONFIGURATION_CTRL_ASSR (0x00000400)
128 #define DP_CONFIGURATION_CTRL_RGB_YUV (0x00000800)
129 #define DP_CONFIGURATION_CTRL_LSCLK_DIV (0x00002000)
130 #define DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT (0x04)
131 #define DP_CONFIGURATION_CTRL_BPC_SHIFT (0x08)
132 #define DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT (0x0D)
134 #define REG_DP_SOFTWARE_MVID (0x00000010)
135 #define REG_DP_SOFTWARE_NVID (0x00000018)
136 #define REG_DP_TOTAL_HOR_VER (0x0000001C)
137 #define REG_DP_START_HOR_VER_FROM_SYNC (0x00000020)
138 #define REG_DP_HSYNC_VSYNC_WIDTH_POLARITY (0x00000024)
139 #define REG_DP_ACTIVE_HOR_VER (0x00000028)
141 #define REG_DP_MISC1_MISC0 (0x0000002C)
142 #define DP_MISC0_SYNCHRONOUS_CLK (0x00000001)
143 #define DP_MISC0_COLORIMETRY_CFG_SHIFT (0x00000001)
144 #define DP_MISC0_TEST_BITS_DEPTH_SHIFT (0x00000005)
146 #define DP_MISC0_COLORIMERY_CFG_LEGACY_RGB (0)
147 #define DP_MISC0_COLORIMERY_CFG_CEA_RGB (0x04)
149 #define REG_DP_VALID_BOUNDARY (0x00000030)
150 #define REG_DP_VALID_BOUNDARY_2 (0x00000034)
152 #define REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING (0x00000038)
153 #define LANE0_MAPPING_SHIFT (0x00000000)
154 #define LANE1_MAPPING_SHIFT (0x00000002)
155 #define LANE2_MAPPING_SHIFT (0x00000004)
156 #define LANE3_MAPPING_SHIFT (0x00000006)
158 #define REG_DP_MAINLINK_READY (0x00000040)
159 #define DP_MAINLINK_READY_FOR_VIDEO (0x00000001)
160 #define DP_MAINLINK_READY_LINK_TRAINING_SHIFT (0x00000003)
162 #define REG_DP_MAINLINK_LEVELS (0x00000044)
163 #define DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2 (0x00000002)
166 #define REG_DP_TU (0x0000004C)
168 #define REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET (0x00000054)
169 #define DP_HBR2_ERM_PATTERN (0x00010000)
171 #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0 (0x000000C0)
172 #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1 (0x000000C4)
173 #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2 (0x000000C8)
175 #define MMSS_DP_MISC1_MISC0 (0x0000002C)
176 #define MMSS_DP_AUDIO_TIMING_GEN (0x00000080)
177 #define MMSS_DP_AUDIO_TIMING_RBR_32 (0x00000084)
178 #define MMSS_DP_AUDIO_TIMING_HBR_32 (0x00000088)
179 #define MMSS_DP_AUDIO_TIMING_RBR_44 (0x0000008C)
180 #define MMSS_DP_AUDIO_TIMING_HBR_44 (0x00000090)
181 #define MMSS_DP_AUDIO_TIMING_RBR_48 (0x00000094)
182 #define MMSS_DP_AUDIO_TIMING_HBR_48 (0x00000098)
184 #define REG_PSR_CONFIG (0x00000100)
185 #define DISABLE_PSR (0x00000000)
186 #define PSR1_SUPPORTED (0x00000001)
187 #define PSR2_WITHOUT_FRAMESYNC (0x00000002)
188 #define PSR2_WITH_FRAMESYNC (0x00000003)
190 #define REG_PSR_CMD (0x00000110)
191 #define PSR_ENTER (0x00000001)
192 #define PSR_EXIT (0x00000002)
194 #define MMSS_DP_PSR_CRC_RG (0x00000154)
195 #define MMSS_DP_PSR_CRC_B (0x00000158)
197 #define REG_DP_COMPRESSION_MODE_CTRL (0x00000180)
199 #define MMSS_DP_AUDIO_CFG (0x00000200)
200 #define MMSS_DP_AUDIO_STATUS (0x00000204)
201 #define MMSS_DP_AUDIO_PKT_CTRL (0x00000208)
202 #define MMSS_DP_AUDIO_PKT_CTRL2 (0x0000020C)
203 #define MMSS_DP_AUDIO_ACR_CTRL (0x00000210)
204 #define MMSS_DP_AUDIO_CTRL_RESET (0x00000214)
206 #define MMSS_DP_SDP_CFG (0x00000228)
207 #define MMSS_DP_SDP_CFG2 (0x0000022C)
208 #define MMSS_DP_AUDIO_TIMESTAMP_0 (0x00000230)
209 #define MMSS_DP_AUDIO_TIMESTAMP_1 (0x00000234)
211 #define MMSS_DP_AUDIO_STREAM_0 (0x00000240)
212 #define MMSS_DP_AUDIO_STREAM_1 (0x00000244)
214 #define MMSS_DP_SDP_CFG3 (0x0000024c)
215 #define UPDATE_SDP (0x00000001)
217 #define MMSS_DP_EXTENSION_0 (0x00000250)
218 #define MMSS_DP_EXTENSION_1 (0x00000254)
219 #define MMSS_DP_EXTENSION_2 (0x00000258)
220 #define MMSS_DP_EXTENSION_3 (0x0000025C)
221 #define MMSS_DP_EXTENSION_4 (0x00000260)
222 #define MMSS_DP_EXTENSION_5 (0x00000264)
223 #define MMSS_DP_EXTENSION_6 (0x00000268)
224 #define MMSS_DP_EXTENSION_7 (0x0000026C)
225 #define MMSS_DP_EXTENSION_8 (0x00000270)
226 #define MMSS_DP_EXTENSION_9 (0x00000274)
227 #define MMSS_DP_AUDIO_COPYMANAGEMENT_0 (0x00000278)
228 #define MMSS_DP_AUDIO_COPYMANAGEMENT_1 (0x0000027C)
229 #define MMSS_DP_AUDIO_COPYMANAGEMENT_2 (0x00000280)
230 #define MMSS_DP_AUDIO_COPYMANAGEMENT_3 (0x00000284)
231 #define MMSS_DP_AUDIO_COPYMANAGEMENT_4 (0x00000288)
232 #define MMSS_DP_AUDIO_COPYMANAGEMENT_5 (0x0000028C)
233 #define MMSS_DP_AUDIO_ISRC_0 (0x00000290)
234 #define MMSS_DP_AUDIO_ISRC_1 (0x00000294)
235 #define MMSS_DP_AUDIO_ISRC_2 (0x00000298)
236 #define MMSS_DP_AUDIO_ISRC_3 (0x0000029C)
237 #define MMSS_DP_AUDIO_ISRC_4 (0x000002A0)
238 #define MMSS_DP_AUDIO_ISRC_5 (0x000002A4)
239 #define MMSS_DP_AUDIO_INFOFRAME_0 (0x000002A8)
240 #define MMSS_DP_AUDIO_INFOFRAME_1 (0x000002AC)
241 #define MMSS_DP_AUDIO_INFOFRAME_2 (0x000002B0)
243 #define MMSS_DP_GENERIC0_0 (0x00000300)
244 #define MMSS_DP_GENERIC0_1 (0x00000304)
245 #define MMSS_DP_GENERIC0_2 (0x00000308)
246 #define MMSS_DP_GENERIC0_3 (0x0000030C)
247 #define MMSS_DP_GENERIC0_4 (0x00000310)
248 #define MMSS_DP_GENERIC0_5 (0x00000314)
249 #define MMSS_DP_GENERIC0_6 (0x00000318)
250 #define MMSS_DP_GENERIC0_7 (0x0000031C)
251 #define MMSS_DP_GENERIC0_8 (0x00000320)
252 #define MMSS_DP_GENERIC0_9 (0x00000324)
253 #define MMSS_DP_GENERIC1_0 (0x00000328)
254 #define MMSS_DP_GENERIC1_1 (0x0000032C)
255 #define MMSS_DP_GENERIC1_2 (0x00000330)
256 #define MMSS_DP_GENERIC1_3 (0x00000334)
257 #define MMSS_DP_GENERIC1_4 (0x00000338)
258 #define MMSS_DP_GENERIC1_5 (0x0000033C)
259 #define MMSS_DP_GENERIC1_6 (0x00000340)
260 #define MMSS_DP_GENERIC1_7 (0x00000344)
261 #define MMSS_DP_GENERIC1_8 (0x00000348)
262 #define MMSS_DP_GENERIC1_9 (0x0000034C)
264 #define MMSS_DP_VSCEXT_0 (0x000002D0)
265 #define MMSS_DP_VSCEXT_1 (0x000002D4)
266 #define MMSS_DP_VSCEXT_2 (0x000002D8)
267 #define MMSS_DP_VSCEXT_3 (0x000002DC)
268 #define MMSS_DP_VSCEXT_4 (0x000002E0)
269 #define MMSS_DP_VSCEXT_5 (0x000002E4)
270 #define MMSS_DP_VSCEXT_6 (0x000002E8)
271 #define MMSS_DP_VSCEXT_7 (0x000002EC)
272 #define MMSS_DP_VSCEXT_8 (0x000002F0)
273 #define MMSS_DP_VSCEXT_9 (0x000002F4)
275 #define MMSS_DP_BIST_ENABLE (0x00000000)
276 #define DP_BIST_ENABLE_DPBIST_EN (0x00000001)
278 #define MMSS_DP_TIMING_ENGINE_EN (0x00000010)
279 #define DP_TIMING_ENGINE_EN_EN (0x00000001)
281 #define MMSS_DP_INTF_CONFIG (0x00000014)
282 #define MMSS_DP_INTF_HSYNC_CTL (0x00000018)
283 #define MMSS_DP_INTF_VSYNC_PERIOD_F0 (0x0000001C)
284 #define MMSS_DP_INTF_VSYNC_PERIOD_F1 (0x00000020)
285 #define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0 (0x00000024)
286 #define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1 (0x00000028)
287 #define MMSS_INTF_DISPLAY_V_START_F0 (0x0000002C)
288 #define MMSS_INTF_DISPLAY_V_START_F1 (0x00000030)
289 #define MMSS_DP_INTF_DISPLAY_V_END_F0 (0x00000034)
290 #define MMSS_DP_INTF_DISPLAY_V_END_F1 (0x00000038)
291 #define MMSS_DP_INTF_ACTIVE_V_START_F0 (0x0000003C)
292 #define MMSS_DP_INTF_ACTIVE_V_START_F1 (0x00000040)
293 #define MMSS_DP_INTF_ACTIVE_V_END_F0 (0x00000044)
294 #define MMSS_DP_INTF_ACTIVE_V_END_F1 (0x00000048)
295 #define MMSS_DP_INTF_DISPLAY_HCTL (0x0000004C)
296 #define MMSS_DP_INTF_ACTIVE_HCTL (0x00000050)
297 #define MMSS_DP_INTF_POLARITY_CTL (0x00000058)
299 #define MMSS_DP_TPG_MAIN_CONTROL (0x00000060)
300 #define MMSS_DP_DSC_DTO (0x0000007C)
301 #define DP_TPG_CHECKERED_RECT_PATTERN (0x00000100)
303 #define MMSS_DP_TPG_VIDEO_CONFIG (0x00000064)
304 #define DP_TPG_VIDEO_CONFIG_BPP_8BIT (0x00000001)
305 #define DP_TPG_VIDEO_CONFIG_RGB (0x00000004)
307 #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088)
309 #define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C)
310 #define REG_DP_PHY_AUX_BIST_CFG (0x00000050)
311 #define REG_DP_PHY_AUX_INTERRUPT_STATUS (0x000000BC)
314 #define DP_HDCP_CTRL (0x0A0)
315 #define DP_HDCP_STATUS (0x0A4)
316 #define DP_HDCP_SW_UPPER_AKSV (0x098)
317 #define DP_HDCP_SW_LOWER_AKSV (0x09C)
318 #define DP_HDCP_ENTROPY_CTRL0 (0x350)
319 #define DP_HDCP_ENTROPY_CTRL1 (0x35C)
320 #define DP_HDCP_SHA_STATUS (0x0C8)
321 #define DP_HDCP_RCVPORT_DATA2_0 (0x0B0)
322 #define DP_HDCP_RCVPORT_DATA3 (0x0A4)
323 #define DP_HDCP_RCVPORT_DATA4 (0x0A8)
324 #define DP_HDCP_RCVPORT_DATA5 (0x0C0)
325 #define DP_HDCP_RCVPORT_DATA6 (0x0C4)
327 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_CTRL (0x024)
328 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_DATA (0x028)
329 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA0 (0x004)
330 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA1 (0x008)
331 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA7 (0x00C)
332 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA8 (0x010)
333 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA9 (0x014)
334 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA10 (0x018)
335 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA11 (0x01C)
336 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA12 (0x020)