Lines Matching refs:scale_cfg
396 struct dpu_hw_scaler3_cfg *scale_cfg, in _dpu_plane_setup_scaler3() argument
412 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = in _dpu_plane_setup_scaler3()
414 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = in _dpu_plane_setup_scaler3()
418 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] = in _dpu_plane_setup_scaler3()
419 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v; in _dpu_plane_setup_scaler3()
420 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] = in _dpu_plane_setup_scaler3()
421 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h; in _dpu_plane_setup_scaler3()
423 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] = in _dpu_plane_setup_scaler3()
424 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2]; in _dpu_plane_setup_scaler3()
425 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] = in _dpu_plane_setup_scaler3()
426 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2]; in _dpu_plane_setup_scaler3()
428 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] = in _dpu_plane_setup_scaler3()
429 scale_cfg->phase_step_x[DPU_SSPP_COMP_0]; in _dpu_plane_setup_scaler3()
430 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] = in _dpu_plane_setup_scaler3()
431 scale_cfg->phase_step_y[DPU_SSPP_COMP_0]; in _dpu_plane_setup_scaler3()
434 scale_cfg->src_width[i] = src_w; in _dpu_plane_setup_scaler3()
435 scale_cfg->src_height[i] = src_h; in _dpu_plane_setup_scaler3()
437 scale_cfg->src_width[i] /= chroma_subsmpl_h; in _dpu_plane_setup_scaler3()
438 scale_cfg->src_height[i] /= chroma_subsmpl_v; in _dpu_plane_setup_scaler3()
443 scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; in _dpu_plane_setup_scaler3()
444 scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; in _dpu_plane_setup_scaler3()
446 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; in _dpu_plane_setup_scaler3()
447 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; in _dpu_plane_setup_scaler3()
454 scale_cfg->dst_width = dst_w; in _dpu_plane_setup_scaler3()
455 scale_cfg->dst_height = dst_h; in _dpu_plane_setup_scaler3()
456 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL; in _dpu_plane_setup_scaler3()
457 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL; in _dpu_plane_setup_scaler3()
458 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL; in _dpu_plane_setup_scaler3()
459 scale_cfg->lut_flag = 0; in _dpu_plane_setup_scaler3()
460 scale_cfg->blend_cfg = 1; in _dpu_plane_setup_scaler3()
461 scale_cfg->enable = 1; in _dpu_plane_setup_scaler3()
464 static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg, in _dpu_plane_setup_pixel_ext() argument