Lines Matching refs:reg_val

61 	u32 reg_val;  in dpu_hw_set_mem_type()  local
79 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
80 reg_val &= ~(0x7 << bit_off); in dpu_hw_set_mem_type()
81 reg_val |= (value & 0x7) << bit_off; in dpu_hw_set_mem_type()
82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
89 u32 reg_val; in dpu_hw_set_limit_conf() local
100 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_limit_conf()
101 reg_val &= ~(0xFF << bit_off); in dpu_hw_set_limit_conf()
102 reg_val |= (limit) << bit_off; in dpu_hw_set_limit_conf()
103 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_limit_conf()
110 u32 reg_val; in dpu_hw_get_limit_conf() local
122 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_get_limit_conf()
123 limit = (reg_val >> bit_off) & 0xFF; in dpu_hw_get_limit_conf()
132 u32 reg_val; in dpu_hw_set_halt_ctrl() local
134 reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL0); in dpu_hw_set_halt_ctrl()
137 reg_val |= BIT(xin_id); in dpu_hw_set_halt_ctrl()
139 reg_val &= ~BIT(xin_id); in dpu_hw_set_halt_ctrl()
141 DPU_REG_WRITE(c, VBIF_XIN_HALT_CTRL0, reg_val); in dpu_hw_set_halt_ctrl()
148 u32 reg_val; in dpu_hw_get_halt_ctrl() local
150 reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL1); in dpu_hw_get_halt_ctrl()
152 return (reg_val & BIT(xin_id)) ? true : false; in dpu_hw_get_halt_ctrl()
159 u32 reg_lvl, reg_val, reg_val_lvl, mask, reg_high, reg_shift; in dpu_hw_set_qos_remap() local
170 reg_val = DPU_REG_READ(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high); in dpu_hw_set_qos_remap()
175 reg_val &= ~mask; in dpu_hw_set_qos_remap()
176 reg_val |= (remap_level << reg_shift) & mask; in dpu_hw_set_qos_remap()
181 DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val); in dpu_hw_set_qos_remap()
188 u32 reg_val; in dpu_hw_set_write_gather_en() local
195 reg_val = DPU_REG_READ(c, VBIF_WRITE_GATHER_EN); in dpu_hw_set_write_gather_en()
196 reg_val |= BIT(xin_id); in dpu_hw_set_write_gather_en()
197 DPU_REG_WRITE(c, VBIF_WRITE_GATHER_EN, reg_val); in dpu_hw_set_write_gather_en()