Lines Matching refs:csc_reg_off
391 u32 csc_reg_off, in dpu_hw_csc_setup() argument
401 DPU_REG_WRITE(c, csc_reg_off, val); in dpu_hw_csc_setup()
404 DPU_REG_WRITE(c, csc_reg_off + 0x4, val); in dpu_hw_csc_setup()
407 DPU_REG_WRITE(c, csc_reg_off + 0x8, val); in dpu_hw_csc_setup()
410 DPU_REG_WRITE(c, csc_reg_off + 0xc, val); in dpu_hw_csc_setup()
412 DPU_REG_WRITE(c, csc_reg_off + 0x10, val); in dpu_hw_csc_setup()
416 DPU_REG_WRITE(c, csc_reg_off + 0x14, val); in dpu_hw_csc_setup()
418 DPU_REG_WRITE(c, csc_reg_off + 0x18, val); in dpu_hw_csc_setup()
420 DPU_REG_WRITE(c, csc_reg_off + 0x1c, val); in dpu_hw_csc_setup()
424 DPU_REG_WRITE(c, csc_reg_off + 0x20, val); in dpu_hw_csc_setup()
426 DPU_REG_WRITE(c, csc_reg_off + 0x24, val); in dpu_hw_csc_setup()
428 DPU_REG_WRITE(c, csc_reg_off + 0x28, val); in dpu_hw_csc_setup()
431 DPU_REG_WRITE(c, csc_reg_off + 0x2c, data->csc_pre_bv[0]); in dpu_hw_csc_setup()
432 DPU_REG_WRITE(c, csc_reg_off + 0x30, data->csc_pre_bv[1]); in dpu_hw_csc_setup()
433 DPU_REG_WRITE(c, csc_reg_off + 0x34, data->csc_pre_bv[2]); in dpu_hw_csc_setup()
436 DPU_REG_WRITE(c, csc_reg_off + 0x38, data->csc_post_bv[0]); in dpu_hw_csc_setup()
437 DPU_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]); in dpu_hw_csc_setup()
438 DPU_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]); in dpu_hw_csc_setup()