Lines Matching refs:pending_flush_mask
81 trace_dpu_hw_ctl_trigger_start(ctx->pending_flush_mask, in dpu_hw_ctl_trigger_start()
93 trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask, in dpu_hw_ctl_trigger_pending()
100 trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask, in dpu_hw_ctl_clear_pending_flush()
102 ctx->pending_flush_mask = 0x0; in dpu_hw_ctl_clear_pending_flush()
116 ctx->pending_flush_mask); in dpu_hw_ctl_update_pending_flush()
117 ctx->pending_flush_mask |= flushbits; in dpu_hw_ctl_update_pending_flush()
122 return ctx->pending_flush_mask; in dpu_hw_ctl_get_pending_flush()
129 if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX)) in dpu_hw_ctl_trigger_flush_v1()
132 if (ctx->pending_flush_mask & BIT(INTF_IDX)) in dpu_hw_ctl_trigger_flush_v1()
135 if (ctx->pending_flush_mask & BIT(WB_IDX)) in dpu_hw_ctl_trigger_flush_v1()
139 if (ctx->pending_flush_mask & BIT(DSPP_IDX)) in dpu_hw_ctl_trigger_flush_v1()
147 if (ctx->pending_flush_mask & BIT(DSC_IDX)) in dpu_hw_ctl_trigger_flush_v1()
151 DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); in dpu_hw_ctl_trigger_flush_v1()
156 trace_dpu_hw_ctl_trigger_pending_flush(ctx->pending_flush_mask, in dpu_hw_ctl_trigger_flush()
158 DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); in dpu_hw_ctl_trigger_flush()
166 ctx->pending_flush_mask |= BIT(0); in dpu_hw_ctl_update_pending_flush_sspp()
169 ctx->pending_flush_mask |= BIT(1); in dpu_hw_ctl_update_pending_flush_sspp()
172 ctx->pending_flush_mask |= BIT(2); in dpu_hw_ctl_update_pending_flush_sspp()
175 ctx->pending_flush_mask |= BIT(18); in dpu_hw_ctl_update_pending_flush_sspp()
178 ctx->pending_flush_mask |= BIT(3); in dpu_hw_ctl_update_pending_flush_sspp()
181 ctx->pending_flush_mask |= BIT(4); in dpu_hw_ctl_update_pending_flush_sspp()
184 ctx->pending_flush_mask |= BIT(5); in dpu_hw_ctl_update_pending_flush_sspp()
187 ctx->pending_flush_mask |= BIT(19); in dpu_hw_ctl_update_pending_flush_sspp()
190 ctx->pending_flush_mask |= BIT(11); in dpu_hw_ctl_update_pending_flush_sspp()
193 ctx->pending_flush_mask |= BIT(12); in dpu_hw_ctl_update_pending_flush_sspp()
196 ctx->pending_flush_mask |= BIT(24); in dpu_hw_ctl_update_pending_flush_sspp()
199 ctx->pending_flush_mask |= BIT(25); in dpu_hw_ctl_update_pending_flush_sspp()
202 ctx->pending_flush_mask |= BIT(13); in dpu_hw_ctl_update_pending_flush_sspp()
205 ctx->pending_flush_mask |= BIT(14); in dpu_hw_ctl_update_pending_flush_sspp()
208 ctx->pending_flush_mask |= BIT(22); in dpu_hw_ctl_update_pending_flush_sspp()
211 ctx->pending_flush_mask |= BIT(23); in dpu_hw_ctl_update_pending_flush_sspp()
223 ctx->pending_flush_mask |= BIT(6); in dpu_hw_ctl_update_pending_flush_mixer()
226 ctx->pending_flush_mask |= BIT(7); in dpu_hw_ctl_update_pending_flush_mixer()
229 ctx->pending_flush_mask |= BIT(8); in dpu_hw_ctl_update_pending_flush_mixer()
232 ctx->pending_flush_mask |= BIT(9); in dpu_hw_ctl_update_pending_flush_mixer()
235 ctx->pending_flush_mask |= BIT(10); in dpu_hw_ctl_update_pending_flush_mixer()
238 ctx->pending_flush_mask |= BIT(20); in dpu_hw_ctl_update_pending_flush_mixer()
244 ctx->pending_flush_mask |= CTL_FLUSH_MASK_CTL; in dpu_hw_ctl_update_pending_flush_mixer()
252 ctx->pending_flush_mask |= BIT(31); in dpu_hw_ctl_update_pending_flush_intf()
255 ctx->pending_flush_mask |= BIT(30); in dpu_hw_ctl_update_pending_flush_intf()
258 ctx->pending_flush_mask |= BIT(29); in dpu_hw_ctl_update_pending_flush_intf()
261 ctx->pending_flush_mask |= BIT(28); in dpu_hw_ctl_update_pending_flush_intf()
275 ctx->pending_flush_mask |= BIT(WB_IDX); in dpu_hw_ctl_update_pending_flush_wb()
286 ctx->pending_flush_mask |= BIT(WB_IDX); in dpu_hw_ctl_update_pending_flush_wb_v1()
293 ctx->pending_flush_mask |= BIT(INTF_IDX); in dpu_hw_ctl_update_pending_flush_intf_v1()
300 ctx->pending_flush_mask |= BIT(MERGE_3D_IDX); in dpu_hw_ctl_update_pending_flush_merge_3d_v1()
307 ctx->pending_flush_mask |= BIT(DSC_IDX); in dpu_hw_ctl_update_pending_flush_dsc_v1()
315 ctx->pending_flush_mask |= BIT(13); in dpu_hw_ctl_update_pending_flush_dspp()
318 ctx->pending_flush_mask |= BIT(14); in dpu_hw_ctl_update_pending_flush_dspp()
321 ctx->pending_flush_mask |= BIT(15); in dpu_hw_ctl_update_pending_flush_dspp()
324 ctx->pending_flush_mask |= BIT(21); in dpu_hw_ctl_update_pending_flush_dspp()
345 ctx->pending_flush_mask |= BIT(DSPP_IDX); in dpu_hw_ctl_update_pending_flush_dspp_sub_blocks()