Lines Matching +full:0 +full:x0003ffff
52 VS_DEALLOC = 0,
119 DI_PT_NONE = 0,
168 DI_SRC_SEL_DMA = 0,
175 DI_FACE_CULL_NONE = 0,
182 INDEX_SIZE_IGN = 0,
183 INDEX_SIZE_16_BIT = 0,
186 INDEX_SIZE_INVALID = 0,
190 IGNORE_VISIBILITY = 0,
195 CP_TYPE0_PKT = 0,
196 CP_TYPE1_PKT = 0x40000000,
197 CP_TYPE2_PKT = 0x80000000,
198 CP_TYPE3_PKT = 0xc0000000,
199 CP_TYPE4_PKT = 0x40000000,
200 CP_TYPE7_PKT = 0x70000000,
338 SB_VERT_TEX = 0,
349 ST_SHADER = 0,
354 SS_DIRECT = 0,
363 SB4_VS_TEX = 0,
380 ST4_SHADER = 0,
386 SS4_DIRECT = 0,
391 SB6_VS_TEX = 0,
408 ST6_SHADER = 0,
415 SS6_DIRECT = 0,
422 INDEX4_SIZE_8_BIT = 0,
428 TESS_QUADS = 0,
445 NE_0_PASS = 0,
450 WRITE_ALWAYS = 0,
469 BLIT_OP_FILL = 0,
490 SMMU_INFO = 0,
504 RESTORE_IB = 0,
523 #define REG_CP_LOAD_STATE_0 0x00000000
524 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
525 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
530 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
536 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
542 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
549 #define REG_CP_LOAD_STATE_1 0x00000001
550 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
551 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
556 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
563 #define REG_CP_LOAD_STATE4_0 0x00000000
564 #define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff
565 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0
570 #define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000
576 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000
582 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000
589 #define REG_CP_LOAD_STATE4_1 0x00000001
590 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003
591 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0
596 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc
603 #define REG_CP_LOAD_STATE4_2 0x00000002
604 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
605 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0
611 #define REG_CP_LOAD_STATE6_0 0x00000000
612 #define CP_LOAD_STATE6_0_DST_OFF__MASK 0x00003fff
613 #define CP_LOAD_STATE6_0_DST_OFF__SHIFT 0
618 #define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x0000c000
624 #define CP_LOAD_STATE6_0_STATE_SRC__MASK 0x00030000
630 #define CP_LOAD_STATE6_0_STATE_BLOCK__MASK 0x003c0000
636 #define CP_LOAD_STATE6_0_NUM_UNIT__MASK 0xffc00000
643 #define REG_CP_LOAD_STATE6_1 0x00000001
644 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK 0xfffffffc
651 #define REG_CP_LOAD_STATE6_2 0x00000002
652 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
653 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT 0
659 #define REG_CP_LOAD_STATE6_EXT_SRC_ADDR 0x00000001
661 #define REG_CP_DRAW_INDX_0 0x00000000
662 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
663 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
669 #define REG_CP_DRAW_INDX_1 0x00000001
670 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
671 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
676 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
682 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
688 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
694 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000
695 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
696 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
697 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000
704 #define REG_CP_DRAW_INDX_2 0x00000002
705 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
706 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
712 #define REG_CP_DRAW_INDX_3 0x00000003
713 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff
714 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0
720 #define REG_CP_DRAW_INDX_4 0x00000004
721 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff
722 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0
728 #define REG_CP_DRAW_INDX_2_0 0x00000000
729 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
730 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
736 #define REG_CP_DRAW_INDX_2_1 0x00000001
737 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
738 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
743 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
749 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
755 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
761 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
762 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
763 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
764 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000
771 #define REG_CP_DRAW_INDX_2_2 0x00000002
772 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
773 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
779 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
780 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
781 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
786 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
792 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300
798 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
804 #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK 0x00003000
810 #define CP_DRAW_INDX_OFFSET_0_GS_ENABLE 0x00010000
811 #define CP_DRAW_INDX_OFFSET_0_TESS_ENABLE 0x00020000
813 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
814 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
815 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0
821 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
822 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
823 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
829 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
830 #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK 0xffffffff
831 #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT 0
838 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
839 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK 0xffffffff
840 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT 0
846 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
847 #define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK 0xffffffff
848 #define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT 0
854 #define REG_CP_DRAW_INDX_OFFSET_INDX_BASE 0x00000004
856 #define REG_CP_DRAW_INDX_OFFSET_6 0x00000006
857 #define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK 0xffffffff
858 #define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT 0
864 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
865 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
866 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
872 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
873 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff
874 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0
880 #define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000
881 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
882 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0
887 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
893 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300
899 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
905 #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK 0x00003000
911 #define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE 0x00010000
912 #define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE 0x00020000
915 #define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001
916 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff
917 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0
924 #define REG_A5XX_CP_DRAW_INDIRECT_1 0x00000001
925 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK 0xffffffff
926 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT 0
932 #define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002
933 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff
934 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0
940 #define REG_A5XX_CP_DRAW_INDIRECT_INDIRECT 0x00000001
942 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000
943 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
944 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0
949 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
955 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300
961 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
967 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK 0x00003000
973 #define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE 0x00010000
974 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE 0x00020000
977 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
978 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff
979 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0
985 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
986 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff
987 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0
993 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
994 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff
995 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0
1002 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
1003 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff
1004 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0
1010 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
1011 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff
1012 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0
1018 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE 0x00000001
1020 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
1021 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff
1022 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0
1028 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004
1029 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff
1030 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0
1036 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005
1037 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff
1038 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0
1044 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT 0x00000004
1046 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 0x00000000
1047 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK 0x0000003f
1048 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT 0
1053 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK 0x000000c0
1059 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK 0x00000300
1065 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK 0x00000c00
1071 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK 0x00003000
1077 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE 0x00010000
1078 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE 0x00020000
1080 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 0x00000001
1081 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK 0x0000000f
1082 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT 0
1087 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK 0x003fff00
1094 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT 0x00000002
1097 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003
1099 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005
1102 #define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDEXED 0x00000003
1104 #define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDEXED 0x00000005
1106 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDEXED 0x00000006
1108 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDEXED 0x00000008
1111 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT 0x00000003
1113 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT 0x00000005
1115 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT 0x00000007
1118 #define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDIRECT_INDEXED 0x00000003
1120 #define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDIRECT_INDEXED 0x00000005
1122 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT_INDEXED 0x00000006
1124 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT_INDEXED 0x00000008
1126 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT_INDEXED 0x0000000a
1128 #define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 0x00000000
1129 #define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE 0x00000001
1131 #define REG_CP_DRAW_PRED_ENABLE_LOCAL_0 0x00000000
1132 #define CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE 0x00000001
1134 #define REG_CP_DRAW_PRED_SET_0 0x00000000
1135 #define CP_DRAW_PRED_SET_0_SRC__MASK 0x000000f0
1141 #define CP_DRAW_PRED_SET_0_TEST__MASK 0x00000100
1148 #define REG_CP_DRAW_PRED_SET_MEM_ADDR 0x00000001
1150 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; } in REG_CP_SET_DRAW_STATE_()
1152 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } in REG_CP_SET_DRAW_STATE__0()
1153 #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
1154 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0
1159 #define CP_SET_DRAW_STATE__0_DIRTY 0x00010000
1160 #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
1161 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
1162 #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
1163 #define CP_SET_DRAW_STATE__0_BINNING 0x00100000
1164 #define CP_SET_DRAW_STATE__0_GMEM 0x00200000
1165 #define CP_SET_DRAW_STATE__0_SYSMEM 0x00400000
1166 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
1173 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } in REG_CP_SET_DRAW_STATE__1()
1174 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff
1175 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0
1181 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } in REG_CP_SET_DRAW_STATE__2()
1182 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff
1183 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0
1189 #define REG_CP_SET_BIN_0 0x00000000
1191 #define REG_CP_SET_BIN_1 0x00000001
1192 #define CP_SET_BIN_1_X1__MASK 0x0000ffff
1193 #define CP_SET_BIN_1_X1__SHIFT 0
1198 #define CP_SET_BIN_1_Y1__MASK 0xffff0000
1205 #define REG_CP_SET_BIN_2 0x00000002
1206 #define CP_SET_BIN_2_X2__MASK 0x0000ffff
1207 #define CP_SET_BIN_2_X2__SHIFT 0
1212 #define CP_SET_BIN_2_Y2__MASK 0xffff0000
1219 #define REG_CP_SET_BIN_DATA_0 0x00000000
1220 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
1221 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
1227 #define REG_CP_SET_BIN_DATA_1 0x00000001
1228 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
1229 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
1235 #define REG_CP_SET_BIN_DATA5_0 0x00000000
1236 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000
1242 #define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000
1249 #define REG_CP_SET_BIN_DATA5_1 0x00000001
1250 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff
1251 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0
1257 #define REG_CP_SET_BIN_DATA5_2 0x00000002
1258 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff
1259 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0
1265 #define REG_CP_SET_BIN_DATA5_3 0x00000003
1266 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff
1267 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0
1273 #define REG_CP_SET_BIN_DATA5_4 0x00000004
1274 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff
1275 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0
1281 #define REG_CP_SET_BIN_DATA5_5 0x00000005
1282 #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK 0xffffffff
1283 #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT 0
1289 #define REG_CP_SET_BIN_DATA5_6 0x00000006
1290 #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK 0xffffffff
1291 #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT 0
1297 #define REG_CP_SET_BIN_DATA5_7 0x00000007
1299 #define REG_CP_SET_BIN_DATA5_9 0x00000009
1301 #define REG_CP_SET_BIN_DATA5_OFFSET_0 0x00000000
1302 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK 0x003f0000
1308 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK 0x07c00000
1315 #define REG_CP_SET_BIN_DATA5_OFFSET_1 0x00000001
1316 #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK 0xffffffff
1317 #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT 0
1323 #define REG_CP_SET_BIN_DATA5_OFFSET_2 0x00000002
1324 #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK 0xffffffff
1325 #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT 0
1331 #define REG_CP_SET_BIN_DATA5_OFFSET_3 0x00000003
1332 #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK 0xffffffff
1333 #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT 0
1339 #define REG_CP_REG_RMW_0 0x00000000
1340 #define CP_REG_RMW_0_DST_REG__MASK 0x0003ffff
1341 #define CP_REG_RMW_0_DST_REG__SHIFT 0
1346 #define CP_REG_RMW_0_ROTATE__MASK 0x1f000000
1352 #define CP_REG_RMW_0_SRC1_ADD 0x20000000
1353 #define CP_REG_RMW_0_SRC1_IS_REG 0x40000000
1354 #define CP_REG_RMW_0_SRC0_IS_REG 0x80000000
1356 #define REG_CP_REG_RMW_1 0x00000001
1357 #define CP_REG_RMW_1_SRC0__MASK 0xffffffff
1358 #define CP_REG_RMW_1_SRC0__SHIFT 0
1364 #define REG_CP_REG_RMW_2 0x00000002
1365 #define CP_REG_RMW_2_SRC1__MASK 0xffffffff
1366 #define CP_REG_RMW_2_SRC1__SHIFT 0
1372 #define REG_CP_REG_TO_MEM_0 0x00000000
1373 #define CP_REG_TO_MEM_0_REG__MASK 0x0003ffff
1374 #define CP_REG_TO_MEM_0_REG__SHIFT 0
1379 #define CP_REG_TO_MEM_0_CNT__MASK 0x3ffc0000
1385 #define CP_REG_TO_MEM_0_64B 0x40000000
1386 #define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
1388 #define REG_CP_REG_TO_MEM_1 0x00000001
1389 #define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
1390 #define CP_REG_TO_MEM_1_DEST__SHIFT 0
1396 #define REG_CP_REG_TO_MEM_2 0x00000002
1397 #define CP_REG_TO_MEM_2_DEST_HI__MASK 0xffffffff
1398 #define CP_REG_TO_MEM_2_DEST_HI__SHIFT 0
1404 #define REG_CP_REG_TO_MEM_OFFSET_REG_0 0x00000000
1405 #define CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK 0x0003ffff
1406 #define CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT 0
1411 #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK 0x3ffc0000
1417 #define CP_REG_TO_MEM_OFFSET_REG_0_64B 0x40000000
1418 #define CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE 0x80000000
1420 #define REG_CP_REG_TO_MEM_OFFSET_REG_1 0x00000001
1421 #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK 0xffffffff
1422 #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT 0
1428 #define REG_CP_REG_TO_MEM_OFFSET_REG_2 0x00000002
1429 #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK 0xffffffff
1430 #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT 0
1436 #define REG_CP_REG_TO_MEM_OFFSET_REG_3 0x00000003
1437 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK 0x0003ffff
1438 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT 0
1443 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH 0x00080000
1445 #define REG_CP_REG_TO_MEM_OFFSET_MEM_0 0x00000000
1446 #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK 0x0003ffff
1447 #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT 0
1452 #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK 0x3ffc0000
1458 #define CP_REG_TO_MEM_OFFSET_MEM_0_64B 0x40000000
1459 #define CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE 0x80000000
1461 #define REG_CP_REG_TO_MEM_OFFSET_MEM_1 0x00000001
1462 #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK 0xffffffff
1463 #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT 0
1469 #define REG_CP_REG_TO_MEM_OFFSET_MEM_2 0x00000002
1470 #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK 0xffffffff
1471 #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT 0
1477 #define REG_CP_REG_TO_MEM_OFFSET_MEM_3 0x00000003
1478 #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK 0xffffffff
1479 #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT 0
1485 #define REG_CP_REG_TO_MEM_OFFSET_MEM_4 0x00000004
1486 #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK 0xffffffff
1487 #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT 0
1493 #define REG_CP_MEM_TO_REG_0 0x00000000
1494 #define CP_MEM_TO_REG_0_REG__MASK 0x0003ffff
1495 #define CP_MEM_TO_REG_0_REG__SHIFT 0
1500 #define CP_MEM_TO_REG_0_CNT__MASK 0x3ff80000
1506 #define CP_MEM_TO_REG_0_SHIFT_BY_2 0x40000000
1507 #define CP_MEM_TO_REG_0_UNK31 0x80000000
1509 #define REG_CP_MEM_TO_REG_1 0x00000001
1510 #define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff
1511 #define CP_MEM_TO_REG_1_SRC__SHIFT 0
1517 #define REG_CP_MEM_TO_REG_2 0x00000002
1518 #define CP_MEM_TO_REG_2_SRC_HI__MASK 0xffffffff
1519 #define CP_MEM_TO_REG_2_SRC_HI__SHIFT 0
1525 #define REG_CP_MEM_TO_MEM_0 0x00000000
1526 #define CP_MEM_TO_MEM_0_NEG_A 0x00000001
1527 #define CP_MEM_TO_MEM_0_NEG_B 0x00000002
1528 #define CP_MEM_TO_MEM_0_NEG_C 0x00000004
1529 #define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
1530 #define CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES 0x40000000
1531 #define CP_MEM_TO_MEM_0_UNK31 0x80000000
1533 #define REG_CP_MEMCPY_0 0x00000000
1534 #define CP_MEMCPY_0_DWORDS__MASK 0xffffffff
1535 #define CP_MEMCPY_0_DWORDS__SHIFT 0
1541 #define REG_CP_MEMCPY_1 0x00000001
1542 #define CP_MEMCPY_1_SRC_LO__MASK 0xffffffff
1543 #define CP_MEMCPY_1_SRC_LO__SHIFT 0
1549 #define REG_CP_MEMCPY_2 0x00000002
1550 #define CP_MEMCPY_2_SRC_HI__MASK 0xffffffff
1551 #define CP_MEMCPY_2_SRC_HI__SHIFT 0
1557 #define REG_CP_MEMCPY_3 0x00000003
1558 #define CP_MEMCPY_3_DST_LO__MASK 0xffffffff
1559 #define CP_MEMCPY_3_DST_LO__SHIFT 0
1565 #define REG_CP_MEMCPY_4 0x00000004
1566 #define CP_MEMCPY_4_DST_HI__MASK 0xffffffff
1567 #define CP_MEMCPY_4_DST_HI__SHIFT 0
1573 #define REG_CP_REG_TO_SCRATCH_0 0x00000000
1574 #define CP_REG_TO_SCRATCH_0_REG__MASK 0x0003ffff
1575 #define CP_REG_TO_SCRATCH_0_REG__SHIFT 0
1580 #define CP_REG_TO_SCRATCH_0_SCRATCH__MASK 0x00700000
1586 #define CP_REG_TO_SCRATCH_0_CNT__MASK 0x07000000
1593 #define REG_CP_SCRATCH_TO_REG_0 0x00000000
1594 #define CP_SCRATCH_TO_REG_0_REG__MASK 0x0003ffff
1595 #define CP_SCRATCH_TO_REG_0_REG__SHIFT 0
1600 #define CP_SCRATCH_TO_REG_0_UNK18 0x00040000
1601 #define CP_SCRATCH_TO_REG_0_SCRATCH__MASK 0x00700000
1607 #define CP_SCRATCH_TO_REG_0_CNT__MASK 0x07000000
1614 #define REG_CP_SCRATCH_WRITE_0 0x00000000
1615 #define CP_SCRATCH_WRITE_0_SCRATCH__MASK 0x00700000
1622 #define REG_CP_MEM_WRITE_0 0x00000000
1623 #define CP_MEM_WRITE_0_ADDR_LO__MASK 0xffffffff
1624 #define CP_MEM_WRITE_0_ADDR_LO__SHIFT 0
1630 #define REG_CP_MEM_WRITE_1 0x00000001
1631 #define CP_MEM_WRITE_1_ADDR_HI__MASK 0xffffffff
1632 #define CP_MEM_WRITE_1_ADDR_HI__SHIFT 0
1638 #define REG_CP_COND_WRITE_0 0x00000000
1639 #define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
1640 #define CP_COND_WRITE_0_FUNCTION__SHIFT 0
1645 #define CP_COND_WRITE_0_POLL_MEMORY 0x00000010
1646 #define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100
1648 #define REG_CP_COND_WRITE_1 0x00000001
1649 #define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff
1650 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0
1656 #define REG_CP_COND_WRITE_2 0x00000002
1657 #define CP_COND_WRITE_2_REF__MASK 0xffffffff
1658 #define CP_COND_WRITE_2_REF__SHIFT 0
1664 #define REG_CP_COND_WRITE_3 0x00000003
1665 #define CP_COND_WRITE_3_MASK__MASK 0xffffffff
1666 #define CP_COND_WRITE_3_MASK__SHIFT 0
1672 #define REG_CP_COND_WRITE_4 0x00000004
1673 #define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff
1674 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0
1680 #define REG_CP_COND_WRITE_5 0x00000005
1681 #define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff
1682 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0
1688 #define REG_CP_COND_WRITE5_0 0x00000000
1689 #define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007
1690 #define CP_COND_WRITE5_0_FUNCTION__SHIFT 0
1695 #define CP_COND_WRITE5_0_SIGNED_COMPARE 0x00000008
1696 #define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010
1697 #define CP_COND_WRITE5_0_POLL_SCRATCH 0x00000020
1698 #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
1700 #define REG_CP_COND_WRITE5_1 0x00000001
1701 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff
1702 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0
1708 #define REG_CP_COND_WRITE5_2 0x00000002
1709 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff
1710 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0
1716 #define REG_CP_COND_WRITE5_3 0x00000003
1717 #define CP_COND_WRITE5_3_REF__MASK 0xffffffff
1718 #define CP_COND_WRITE5_3_REF__SHIFT 0
1724 #define REG_CP_COND_WRITE5_4 0x00000004
1725 #define CP_COND_WRITE5_4_MASK__MASK 0xffffffff
1726 #define CP_COND_WRITE5_4_MASK__SHIFT 0
1732 #define REG_CP_COND_WRITE5_5 0x00000005
1733 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff
1734 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0
1740 #define REG_CP_COND_WRITE5_6 0x00000006
1741 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff
1742 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0
1748 #define REG_CP_COND_WRITE5_7 0x00000007
1749 #define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff
1750 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0
1756 #define REG_CP_WAIT_MEM_GTE_0 0x00000000
1757 #define CP_WAIT_MEM_GTE_0_RESERVED__MASK 0xffffffff
1758 #define CP_WAIT_MEM_GTE_0_RESERVED__SHIFT 0
1764 #define REG_CP_WAIT_MEM_GTE_1 0x00000001
1765 #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK 0xffffffff
1766 #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT 0
1772 #define REG_CP_WAIT_MEM_GTE_2 0x00000002
1773 #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK 0xffffffff
1774 #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT 0
1780 #define REG_CP_WAIT_MEM_GTE_3 0x00000003
1781 #define CP_WAIT_MEM_GTE_3_REF__MASK 0xffffffff
1782 #define CP_WAIT_MEM_GTE_3_REF__SHIFT 0
1788 #define REG_CP_WAIT_REG_MEM_0 0x00000000
1789 #define CP_WAIT_REG_MEM_0_FUNCTION__MASK 0x00000007
1790 #define CP_WAIT_REG_MEM_0_FUNCTION__SHIFT 0
1795 #define CP_WAIT_REG_MEM_0_SIGNED_COMPARE 0x00000008
1796 #define CP_WAIT_REG_MEM_0_POLL_MEMORY 0x00000010
1797 #define CP_WAIT_REG_MEM_0_POLL_SCRATCH 0x00000020
1798 #define CP_WAIT_REG_MEM_0_WRITE_MEMORY 0x00000100
1800 #define REG_CP_WAIT_REG_MEM_1 0x00000001
1801 #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK 0xffffffff
1802 #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT 0
1808 #define REG_CP_WAIT_REG_MEM_2 0x00000002
1809 #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK 0xffffffff
1810 #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT 0
1816 #define REG_CP_WAIT_REG_MEM_3 0x00000003
1817 #define CP_WAIT_REG_MEM_3_REF__MASK 0xffffffff
1818 #define CP_WAIT_REG_MEM_3_REF__SHIFT 0
1824 #define REG_CP_WAIT_REG_MEM_4 0x00000004
1825 #define CP_WAIT_REG_MEM_4_MASK__MASK 0xffffffff
1826 #define CP_WAIT_REG_MEM_4_MASK__SHIFT 0
1832 #define REG_CP_WAIT_REG_MEM_5 0x00000005
1833 #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK 0xffffffff
1834 #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT 0
1840 #define REG_CP_WAIT_TWO_REGS_0 0x00000000
1841 #define CP_WAIT_TWO_REGS_0_REG0__MASK 0x0003ffff
1842 #define CP_WAIT_TWO_REGS_0_REG0__SHIFT 0
1848 #define REG_CP_WAIT_TWO_REGS_1 0x00000001
1849 #define CP_WAIT_TWO_REGS_1_REG1__MASK 0x0003ffff
1850 #define CP_WAIT_TWO_REGS_1_REG1__SHIFT 0
1856 #define REG_CP_WAIT_TWO_REGS_2 0x00000002
1857 #define CP_WAIT_TWO_REGS_2_REF__MASK 0xffffffff
1858 #define CP_WAIT_TWO_REGS_2_REF__SHIFT 0
1864 #define REG_CP_DISPATCH_COMPUTE_0 0x00000000
1866 #define REG_CP_DISPATCH_COMPUTE_1 0x00000001
1867 #define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff
1868 #define CP_DISPATCH_COMPUTE_1_X__SHIFT 0
1874 #define REG_CP_DISPATCH_COMPUTE_2 0x00000002
1875 #define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff
1876 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0
1882 #define REG_CP_DISPATCH_COMPUTE_3 0x00000003
1883 #define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff
1884 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0
1890 #define REG_CP_SET_RENDER_MODE_0 0x00000000
1891 #define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff
1892 #define CP_SET_RENDER_MODE_0_MODE__SHIFT 0
1898 #define REG_CP_SET_RENDER_MODE_1 0x00000001
1899 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff
1900 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0
1906 #define REG_CP_SET_RENDER_MODE_2 0x00000002
1907 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff
1908 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0
1914 #define REG_CP_SET_RENDER_MODE_3 0x00000003
1915 #define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008
1916 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
1918 #define REG_CP_SET_RENDER_MODE_4 0x00000004
1920 #define REG_CP_SET_RENDER_MODE_5 0x00000005
1921 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff
1922 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0
1928 #define REG_CP_SET_RENDER_MODE_6 0x00000006
1929 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff
1930 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0
1936 #define REG_CP_SET_RENDER_MODE_7 0x00000007
1937 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff
1938 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0
1944 #define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000
1945 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff
1946 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0
1952 #define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001
1953 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff
1954 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0
1960 #define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
1962 #define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
1963 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK 0xffffffff
1964 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT 0
1970 #define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
1972 #define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
1973 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
1974 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0
1980 #define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006
1981 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff
1982 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0
1988 #define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007
1990 #define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
1992 #define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
1993 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff
1994 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0
2000 #define REG_CP_PERFCOUNTER_ACTION_2 0x00000002
2001 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff
2002 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0
2008 #define REG_CP_EVENT_WRITE_0 0x00000000
2009 #define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff
2010 #define CP_EVENT_WRITE_0_EVENT__SHIFT 0
2015 #define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000
2016 #define CP_EVENT_WRITE_0_IRQ 0x80000000
2018 #define REG_CP_EVENT_WRITE_1 0x00000001
2019 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
2020 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0
2026 #define REG_CP_EVENT_WRITE_2 0x00000002
2027 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff
2028 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0
2034 #define REG_CP_EVENT_WRITE_3 0x00000003
2036 #define REG_CP_BLIT_0 0x00000000
2037 #define CP_BLIT_0_OP__MASK 0x0000000f
2038 #define CP_BLIT_0_OP__SHIFT 0
2044 #define REG_CP_BLIT_1 0x00000001
2045 #define CP_BLIT_1_SRC_X1__MASK 0x00003fff
2046 #define CP_BLIT_1_SRC_X1__SHIFT 0
2051 #define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000
2058 #define REG_CP_BLIT_2 0x00000002
2059 #define CP_BLIT_2_SRC_X2__MASK 0x00003fff
2060 #define CP_BLIT_2_SRC_X2__SHIFT 0
2065 #define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000
2072 #define REG_CP_BLIT_3 0x00000003
2073 #define CP_BLIT_3_DST_X1__MASK 0x00003fff
2074 #define CP_BLIT_3_DST_X1__SHIFT 0
2079 #define CP_BLIT_3_DST_Y1__MASK 0x3fff0000
2086 #define REG_CP_BLIT_4 0x00000004
2087 #define CP_BLIT_4_DST_X2__MASK 0x00003fff
2088 #define CP_BLIT_4_DST_X2__SHIFT 0
2093 #define CP_BLIT_4_DST_Y2__MASK 0x3fff0000
2100 #define REG_CP_EXEC_CS_0 0x00000000
2102 #define REG_CP_EXEC_CS_1 0x00000001
2103 #define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff
2104 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0
2110 #define REG_CP_EXEC_CS_2 0x00000002
2111 #define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff
2112 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0
2118 #define REG_CP_EXEC_CS_3 0x00000003
2119 #define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff
2120 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0
2126 #define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000
2129 #define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001
2130 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff
2131 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0
2137 #define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002
2138 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc
2144 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000
2150 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000
2158 #define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001
2159 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff
2160 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0
2166 #define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002
2167 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff
2168 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0
2174 #define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003
2175 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc
2181 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000
2187 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000
2194 #define REG_A6XX_CP_SET_MARKER_0 0x00000000
2195 #define A6XX_CP_SET_MARKER_0_MODE__MASK 0x000001ff
2196 #define A6XX_CP_SET_MARKER_0_MODE__SHIFT 0
2201 #define A6XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f
2202 #define A6XX_CP_SET_MARKER_0_MARKER__SHIFT 0
2208 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; } in REG_A6XX_CP_SET_PSEUDO_REG_()
2210 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } in REG_A6XX_CP_SET_PSEUDO_REG__0()
2211 #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007
2212 #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0
2218 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } in REG_A6XX_CP_SET_PSEUDO_REG__1()
2219 #define A6XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff
2220 #define A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0
2226 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } in REG_A6XX_CP_SET_PSEUDO_REG__2()
2227 #define A6XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff
2228 #define A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0
2234 #define REG_A6XX_CP_REG_TEST_0 0x00000000
2235 #define A6XX_CP_REG_TEST_0_REG__MASK 0x0003ffff
2236 #define A6XX_CP_REG_TEST_0_REG__SHIFT 0
2241 #define A6XX_CP_REG_TEST_0_BIT__MASK 0x01f00000
2247 #define A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME 0x02000000
2248 #define A6XX_CP_REG_TEST_0_PRED_BIT__MASK 0x7c000000
2254 #define A6XX_CP_REG_TEST_0_PRED_UPDATE 0x80000000
2256 #define REG_A6XX_CP_REG_TEST_PRED_MASK 0x00000001
2258 #define REG_A6XX_CP_REG_TEST_PRED_VAL 0x00000002
2260 #define REG_CP_COND_REG_EXEC_0 0x00000000
2261 #define CP_COND_REG_EXEC_0_REG0__MASK 0x0003ffff
2262 #define CP_COND_REG_EXEC_0_REG0__SHIFT 0
2267 #define CP_COND_REG_EXEC_0_PRED_BIT__MASK 0x007c0000
2273 #define CP_COND_REG_EXEC_0_BINNING 0x02000000
2274 #define CP_COND_REG_EXEC_0_GMEM 0x04000000
2275 #define CP_COND_REG_EXEC_0_SYSMEM 0x08000000
2276 #define CP_COND_REG_EXEC_0_MODE__MASK 0xf0000000
2283 #define REG_CP_COND_REG_EXEC_1 0x00000001
2284 #define CP_COND_REG_EXEC_1_DWORDS__MASK 0xffffffff
2285 #define CP_COND_REG_EXEC_1_DWORDS__SHIFT 0
2291 #define REG_CP_COND_EXEC_0 0x00000000
2292 #define CP_COND_EXEC_0_ADDR0_LO__MASK 0xffffffff
2293 #define CP_COND_EXEC_0_ADDR0_LO__SHIFT 0
2299 #define REG_CP_COND_EXEC_1 0x00000001
2300 #define CP_COND_EXEC_1_ADDR0_HI__MASK 0xffffffff
2301 #define CP_COND_EXEC_1_ADDR0_HI__SHIFT 0
2307 #define REG_CP_COND_EXEC_2 0x00000002
2308 #define CP_COND_EXEC_2_ADDR1_LO__MASK 0xffffffff
2309 #define CP_COND_EXEC_2_ADDR1_LO__SHIFT 0
2315 #define REG_CP_COND_EXEC_3 0x00000003
2316 #define CP_COND_EXEC_3_ADDR1_HI__MASK 0xffffffff
2317 #define CP_COND_EXEC_3_ADDR1_HI__SHIFT 0
2323 #define REG_CP_COND_EXEC_4 0x00000004
2324 #define CP_COND_EXEC_4_REF__MASK 0xffffffff
2325 #define CP_COND_EXEC_4_REF__SHIFT 0
2331 #define REG_CP_COND_EXEC_5 0x00000005
2332 #define CP_COND_EXEC_5_DWORDS__MASK 0xffffffff
2333 #define CP_COND_EXEC_5_DWORDS__SHIFT 0
2339 #define REG_CP_SET_CTXSWITCH_IB_0 0x00000000
2340 #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK 0xffffffff
2341 #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT 0
2347 #define REG_CP_SET_CTXSWITCH_IB_1 0x00000001
2348 #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK 0xffffffff
2349 #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT 0
2355 #define REG_CP_SET_CTXSWITCH_IB_2 0x00000002
2356 #define CP_SET_CTXSWITCH_IB_2_DWORDS__MASK 0x000fffff
2357 #define CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT 0
2362 #define CP_SET_CTXSWITCH_IB_2_TYPE__MASK 0x00300000
2369 #define REG_CP_REG_WRITE_0 0x00000000
2370 #define CP_REG_WRITE_0_TRACKER__MASK 0x0000000f
2371 #define CP_REG_WRITE_0_TRACKER__SHIFT 0
2377 #define REG_CP_REG_WRITE_1 0x00000001
2379 #define REG_CP_REG_WRITE_2 0x00000002
2381 #define REG_CP_SMMU_TABLE_UPDATE_0 0x00000000
2382 #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK 0xffffffff
2383 #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT 0
2389 #define REG_CP_SMMU_TABLE_UPDATE_1 0x00000001
2390 #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK 0x0000ffff
2391 #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT 0
2396 #define CP_SMMU_TABLE_UPDATE_1_ASID__MASK 0xffff0000
2403 #define REG_CP_SMMU_TABLE_UPDATE_2 0x00000002
2404 #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK 0xffffffff
2405 #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT 0
2411 #define REG_CP_SMMU_TABLE_UPDATE_3 0x00000003
2412 #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK 0xffffffff
2413 #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT 0
2419 #define REG_CP_START_BIN_BIN_COUNT 0x00000000
2421 #define REG_CP_START_BIN_PREFIX_ADDR 0x00000001
2423 #define REG_CP_START_BIN_PREFIX_DWORDS 0x00000003
2425 #define REG_CP_START_BIN_BODY_DWORDS 0x00000004
2427 #define REG_CP_WAIT_TIMESTAMP_0 0x00000000
2429 #define REG_CP_WAIT_TIMESTAMP_ADDR 0x00000001
2431 #define REG_CP_WAIT_TIMESTAMP_TIMESTAMP 0x00000003
2433 #define REG_CP_THREAD_CONTROL_0 0x00000000
2434 #define CP_THREAD_CONTROL_0_THREAD__MASK 0x00000003
2435 #define CP_THREAD_CONTROL_0_THREAD__SHIFT 0
2440 #define CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE 0x08000000
2441 #define CP_THREAD_CONTROL_0_SYNC_THREADS 0x80000000