23 	/* Check that the GMU is idle */  in _a6xx_check_idle()
24 	if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu))  in _a6xx_check_idle()
186 	 * For PM4 the GMU register offsets are calculated from the base of the  in a6xx_submit()
702 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;  in a6xx_set_hwcg()  local
725 		gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);  in a6xx_set_hwcg()
732 		gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);  in a6xx_set_hwcg()
1199 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;  in hw_init()  local
1203 		/* Make sure the GMU keeps the GPU on while we set it up */  in hw_init()
1204 		ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);  in hw_init()
1225 		a6xx_sptprac_enable(gmu);  in hw_init()
1358 	/* Set up the CX GMU counter 0 to count busy ticks */  in hw_init()
1359 	gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);  in hw_init()
1362 	gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5));  in hw_init()
1363 	gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);  in hw_init()
1457 	 * Tell the GMU that we are done touching the GPU and it can start power  in hw_init()
1460 	a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);  in hw_init()
1462 	if (a6xx_gpu->gmu.legacy) {  in hw_init()
1463 		/* Take the GMU out of its special boot mode */  in hw_init()
1464 		a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);  in hw_init()
1476 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_hw_init()
1478 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_hw_init()
1494 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;  in a6xx_recover()  local
1536 	reinit_completion(&gmu->pd_gate);  in a6xx_recover()
1537 	dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb);  in a6xx_recover()
1538 	dev_pm_genpd_synced_poweroff(gmu->cxpd);  in a6xx_recover()
1547 	if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000)))  in a6xx_recover()
1550 	dev_pm_genpd_remove_notifier(gmu->cxpd);  in a6xx_recover()
1687 		gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);  in a6xx_fault_detect_irq()
1808 	/* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */  in a6xx_llc_slices_destroy()
1821 	/* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */  in a6xx_llc_slices_init()
1915 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_pm_resume()
1917 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_pm_resume()
1932 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;  in a6xx_pm_resume()  local
1941 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_pm_resume()
1953 	pm_runtime_resume_and_get(gmu->dev);  in a6xx_pm_resume()
1954 	pm_runtime_resume_and_get(gmu->gxpd);  in a6xx_pm_resume()
1961 		a6xx_sptprac_enable(gmu);  in a6xx_pm_resume()
1966 		pm_runtime_put(gmu->gxpd);  in a6xx_pm_resume()
1967 		pm_runtime_put(gmu->dev);  in a6xx_pm_resume()
1971 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_pm_resume()
1991 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_pm_suspend()
1993 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_pm_suspend()
2010 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;  in a6xx_pm_suspend()  local
2017 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_pm_suspend()
2023 		a6xx_sptprac_disable(gmu);  in a6xx_pm_suspend()
2027 	pm_runtime_put_sync(gmu->gxpd);  in a6xx_pm_suspend()
2029 	pm_runtime_put_sync(gmu->dev);  in a6xx_pm_suspend()
2031 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_pm_suspend()
2047 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_get_timestamp()
2050 	a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);  in a6xx_gmu_get_timestamp()
2054 	a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);  in a6xx_gmu_get_timestamp()
2056 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_get_timestamp()
2108 	busy_cycles = gmu_read64(&a6xx_gpu->gmu,  in a6xx_gpu_busy()
2121 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_gpu_set_freq()
2123 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_gpu_set_freq()
2328 	mutex_init(&a6xx_gpu->gmu.lock);  in a6xx_gpu_init()
2332 	/* Check if there is a GMU phandle and set it up */  in a6xx_gpu_init()
2333 	node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);  in a6xx_gpu_init()
2337 	adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper");  in a6xx_gpu_init()