100 	TILE4_LINEAR = 0,
259 	DEPTH4_NONE = 0,
266 	CCU_BUSY_CYCLES = 0,
285 	CP_ALWAYS_COUNT = 0,
329 	RAS_SUPER_TILES = 0,
346 	TSE_INPUT_PRIM = 0,
366 	HLSQ_SP_VS_STAGE_CONSTANT = 0,
394 	PC_VIS_STREAMS_LOADED = 0,
437 	PWR_CORE_CLOCK_CYCLES = 0,
442 	RB_BUSY_CYCLES = 0,
494 	RBBM_ALWAYS_ON = 0,
526 	SP_LM_LOAD_INSTRUCTIONS = 0,
587 	TP_L1_REQUESTS = 0,
610 	UCHE_VBIF_READ_BEATS_TP = 0,
644 	AXI_READ_REQUESTS_ID_0 = 0,
759 	VFD_UCHE_BYTE_FETCHED = 0,
797 	VSC_BUSY_CYCLES = 0,
805 	A4XX_TEX_NEAREST = 0,
811 	A4XX_TEX_REPEAT = 0,
819 	A4XX_TEX_ANISO_1 = 0,
827 	A4XX_TEX_X = 0,
836 	A4XX_TEX_1D = 0,
843 #define A4XX_CGC_HLSQ_EARLY_CYC__MASK				0x00700000
849 #define A4XX_INT0_RBBM_GPU_IDLE					0x00000001
850 #define A4XX_INT0_RBBM_AHB_ERROR				0x00000002
851 #define A4XX_INT0_RBBM_REG_TIMEOUT				0x00000004
852 #define A4XX_INT0_RBBM_ME_MS_TIMEOUT				0x00000008
853 #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT				0x00000010
854 #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW				0x00000020
855 #define A4XX_INT0_VFD_ERROR					0x00000040
856 #define A4XX_INT0_CP_SW_INT					0x00000080
857 #define A4XX_INT0_CP_T0_PACKET_IN_IB				0x00000100
858 #define A4XX_INT0_CP_OPCODE_ERROR				0x00000200
859 #define A4XX_INT0_CP_RESERVED_BIT_ERROR				0x00000400
860 #define A4XX_INT0_CP_HW_FAULT					0x00000800
861 #define A4XX_INT0_CP_DMA					0x00001000
862 #define A4XX_INT0_CP_IB2_INT					0x00002000
863 #define A4XX_INT0_CP_IB1_INT					0x00004000
864 #define A4XX_INT0_CP_RB_INT					0x00008000
865 #define A4XX_INT0_CP_REG_PROTECT_FAULT				0x00010000
866 #define A4XX_INT0_CP_RB_DONE_TS					0x00020000
867 #define A4XX_INT0_CP_VS_DONE_TS					0x00040000
868 #define A4XX_INT0_CP_PS_DONE_TS					0x00080000
869 #define A4XX_INT0_CACHE_FLUSH_TS				0x00100000
870 #define A4XX_INT0_CP_AHB_ERROR_HALT				0x00200000
871 #define A4XX_INT0_MISC_HANG_DETECT				0x01000000
872 #define A4XX_INT0_UCHE_OOB_ACCESS				0x02000000
873 #define REG_A4XX_RB_GMEM_BASE_ADDR				0x00000cc0
875 #define REG_A4XX_RB_PERFCTR_RB_SEL_0				0x00000cc7
877 #define REG_A4XX_RB_PERFCTR_RB_SEL_1				0x00000cc8
879 #define REG_A4XX_RB_PERFCTR_RB_SEL_2				0x00000cc9
881 #define REG_A4XX_RB_PERFCTR_RB_SEL_3				0x00000cca
883 #define REG_A4XX_RB_PERFCTR_RB_SEL_4				0x00000ccb
885 #define REG_A4XX_RB_PERFCTR_RB_SEL_5				0x00000ccc
887 #define REG_A4XX_RB_PERFCTR_RB_SEL_6				0x00000ccd
889 #define REG_A4XX_RB_PERFCTR_RB_SEL_7				0x00000cce
891 #define REG_A4XX_RB_PERFCTR_CCU_SEL_0				0x00000ccf
893 #define REG_A4XX_RB_PERFCTR_CCU_SEL_1				0x00000cd0
895 #define REG_A4XX_RB_PERFCTR_CCU_SEL_2				0x00000cd1
897 #define REG_A4XX_RB_PERFCTR_CCU_SEL_3				0x00000cd2
899 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION			0x00000ce0
900 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK		0x00003fff
901 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT		0
906 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK		0x3fff0000
913 #define REG_A4XX_RB_CLEAR_COLOR_DW0				0x000020cc
915 #define REG_A4XX_RB_CLEAR_COLOR_DW1				0x000020cd
917 #define REG_A4XX_RB_CLEAR_COLOR_DW2				0x000020ce
919 #define REG_A4XX_RB_CLEAR_COLOR_DW3				0x000020cf
921 #define REG_A4XX_RB_MODE_CONTROL				0x000020a0
922 #define A4XX_RB_MODE_CONTROL_WIDTH__MASK			0x0000003f
923 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT			0
928 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK			0x00003f00
934 #define A4XX_RB_MODE_CONTROL_ENABLE_GMEM			0x00010000
936 #define REG_A4XX_RB_RENDER_CONTROL				0x000020a1
937 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS			0x00000001
938 #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE		0x00000020
940 #define REG_A4XX_RB_MSAA_CONTROL				0x000020a2
941 #define A4XX_RB_MSAA_CONTROL_DISABLE				0x00001000
942 #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK			0x0000e000
949 #define REG_A4XX_RB_RENDER_CONTROL2				0x000020a3
950 #define A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK		0x0000000f
951 #define A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT		0
956 #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK			0x00000010
957 #define A4XX_RB_RENDER_CONTROL2_FACENESS			0x00000020
958 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID			0x00000040
959 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK		0x00000380
965 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR			0x00000800
966 #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_PIXEL			0x00001000
967 #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_CENTROID		0x00002000
968 #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_SAMPLE			0x00004000
969 #define A4XX_RB_RENDER_CONTROL2_SIZE				0x00008000
971 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }  in REG_A4XX_RB_MRT()
973 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }  in REG_A4XX_RB_MRT_CONTROL()
974 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE			0x00000008
975 #define A4XX_RB_MRT_CONTROL_BLEND				0x00000010
976 #define A4XX_RB_MRT_CONTROL_BLEND2				0x00000020
977 #define A4XX_RB_MRT_CONTROL_ROP_ENABLE				0x00000040
978 #define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK			0x00000f00
984 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK		0x0f000000
991 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }  in REG_A4XX_RB_MRT_BUF_INFO()
992 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK			0x0000003f
993 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT		0
998 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK		0x000000c0
1004 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK			0x00000600
1010 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK			0x00001800
1016 #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB				0x00002000
1017 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK		0xffffc000
1024 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }  in REG_A4XX_RB_MRT_BASE()
1026 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }  in REG_A4XX_RB_MRT_CONTROL3()
1027 #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK			0x03fffff8
1034 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }  in REG_A4XX_RB_MRT_BLEND_CONTROL()
1035 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK		0x0000001f
1036 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT		0
1041 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK	0x000000e0
1047 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK		0x00001f00
1053 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK	0x001f0000
1059 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK	0x00e00000
1065 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK	0x1f000000
1072 #define REG_A4XX_RB_BLEND_RED					0x000020f0
1073 #define A4XX_RB_BLEND_RED_UINT__MASK				0x000000ff
1074 #define A4XX_RB_BLEND_RED_UINT__SHIFT				0
1079 #define A4XX_RB_BLEND_RED_SINT__MASK				0x0000ff00
1085 #define A4XX_RB_BLEND_RED_FLOAT__MASK				0xffff0000
1092 #define REG_A4XX_RB_BLEND_RED_F32				0x000020f1
1093 #define A4XX_RB_BLEND_RED_F32__MASK				0xffffffff
1094 #define A4XX_RB_BLEND_RED_F32__SHIFT				0
1100 #define REG_A4XX_RB_BLEND_GREEN					0x000020f2
1101 #define A4XX_RB_BLEND_GREEN_UINT__MASK				0x000000ff
1102 #define A4XX_RB_BLEND_GREEN_UINT__SHIFT				0
1107 #define A4XX_RB_BLEND_GREEN_SINT__MASK				0x0000ff00
1113 #define A4XX_RB_BLEND_GREEN_FLOAT__MASK				0xffff0000
1120 #define REG_A4XX_RB_BLEND_GREEN_F32				0x000020f3
1121 #define A4XX_RB_BLEND_GREEN_F32__MASK				0xffffffff
1122 #define A4XX_RB_BLEND_GREEN_F32__SHIFT				0
1128 #define REG_A4XX_RB_BLEND_BLUE					0x000020f4
1129 #define A4XX_RB_BLEND_BLUE_UINT__MASK				0x000000ff
1130 #define A4XX_RB_BLEND_BLUE_UINT__SHIFT				0
1135 #define A4XX_RB_BLEND_BLUE_SINT__MASK				0x0000ff00
1141 #define A4XX_RB_BLEND_BLUE_FLOAT__MASK				0xffff0000
1148 #define REG_A4XX_RB_BLEND_BLUE_F32				0x000020f5
1149 #define A4XX_RB_BLEND_BLUE_F32__MASK				0xffffffff
1150 #define A4XX_RB_BLEND_BLUE_F32__SHIFT				0
1156 #define REG_A4XX_RB_BLEND_ALPHA					0x000020f6
1157 #define A4XX_RB_BLEND_ALPHA_UINT__MASK				0x000000ff
1158 #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT				0
1163 #define A4XX_RB_BLEND_ALPHA_SINT__MASK				0x0000ff00
1169 #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK				0xffff0000
1176 #define REG_A4XX_RB_BLEND_ALPHA_F32				0x000020f7
1177 #define A4XX_RB_BLEND_ALPHA_F32__MASK				0xffffffff
1178 #define A4XX_RB_BLEND_ALPHA_F32__SHIFT				0
1184 #define REG_A4XX_RB_ALPHA_CONTROL				0x000020f8
1185 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK			0x000000ff
1186 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT			0
1191 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST			0x00000100
1192 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK		0x00000e00
1199 #define REG_A4XX_RB_FS_OUTPUT					0x000020f9
1200 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK			0x000000ff
1201 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT			0
1206 #define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND			0x00000100
1207 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK			0xffff0000
1214 #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL			0x000020fa
1215 #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY			0x00000002
1216 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK			0xfffffffc
1223 #define REG_A4XX_RB_RENDER_COMPONENTS				0x000020fb
1224 #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK			0x0000000f
1225 #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT			0
1230 #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK			0x000000f0
1236 #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK			0x00000f00
1242 #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK			0x0000f000
1248 #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK			0x000f0000
1254 #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK			0x00f00000
1260 #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK			0x0f000000
1266 #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK			0xf0000000
1273 #define REG_A4XX_RB_COPY_CONTROL				0x000020fc
1274 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK			0x00000003
1275 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT		0
1280 #define A4XX_RB_COPY_CONTROL_MODE__MASK				0x00000070
1286 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK			0x00000f00
1292 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK			0xffffc000
1299 #define REG_A4XX_RB_COPY_DEST_BASE				0x000020fd
1300 #define A4XX_RB_COPY_DEST_BASE_BASE__MASK			0xffffffe0
1307 #define REG_A4XX_RB_COPY_DEST_PITCH				0x000020fe
1308 #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK			0xffffffff
1309 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT			0
1315 #define REG_A4XX_RB_COPY_DEST_INFO				0x000020ff
1316 #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK			0x000000fc
1322 #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK			0x00000300
1328 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK		0x00000c00
1334 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK		0x0003c000
1340 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK			0x001c0000
1346 #define A4XX_RB_COPY_DEST_INFO_TILE__MASK			0x03000000
1353 #define REG_A4XX_RB_FS_OUTPUT_REG				0x00002100
1354 #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK				0x0000000f
1355 #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT			0
1360 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z			0x00000020
1362 #define REG_A4XX_RB_DEPTH_CONTROL				0x00002101
1363 #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z			0x00000001
1364 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE			0x00000002
1365 #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE			0x00000004
1366 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK			0x00000070
1372 #define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE			0x00000080
1373 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE			0x00010000
1374 #define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS			0x00020000
1375 #define A4XX_RB_DEPTH_CONTROL_Z_READ_ENABLE			0x80000000
1377 #define REG_A4XX_RB_DEPTH_CLEAR					0x00002102
1379 #define REG_A4XX_RB_DEPTH_INFO					0x00002103
1380 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK			0x00000003
1381 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT			0
1386 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK			0xfffff000
1393 #define REG_A4XX_RB_DEPTH_PITCH					0x00002104
1394 #define A4XX_RB_DEPTH_PITCH__MASK				0xffffffff
1395 #define A4XX_RB_DEPTH_PITCH__SHIFT				0
1401 #define REG_A4XX_RB_DEPTH_PITCH2				0x00002105
1402 #define A4XX_RB_DEPTH_PITCH2__MASK				0xffffffff
1403 #define A4XX_RB_DEPTH_PITCH2__SHIFT				0
1409 #define REG_A4XX_RB_STENCIL_CONTROL				0x00002106
1410 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE			0x00000001
1411 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF		0x00000002
1412 #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ			0x00000004
1413 #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK			0x00000700
1419 #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK			0x00003800
1425 #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK			0x0001c000
1431 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK			0x000e0000
1437 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK			0x00700000
1443 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK			0x03800000
1449 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK			0x1c000000
1455 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK			0xe0000000
1462 #define REG_A4XX_RB_STENCIL_CONTROL2				0x00002107
1463 #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER			0x00000001
1465 #define REG_A4XX_RB_STENCIL_INFO				0x00002108
1466 #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL			0x00000001
1467 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK			0xfffff000
1474 #define REG_A4XX_RB_STENCIL_PITCH				0x00002109
1475 #define A4XX_RB_STENCIL_PITCH__MASK				0xffffffff
1476 #define A4XX_RB_STENCIL_PITCH__SHIFT				0
1482 #define REG_A4XX_RB_STENCILREFMASK				0x0000210b
1483 #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK			0x000000ff
1484 #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT		0
1489 #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK		0x0000ff00
1495 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK		0x00ff0000
1502 #define REG_A4XX_RB_STENCILREFMASK_BF				0x0000210c
1503 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK		0x000000ff
1504 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT		0
1509 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK		0x0000ff00
1515 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK	0x00ff0000
1522 #define REG_A4XX_RB_BIN_OFFSET					0x0000210d
1523 #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE		0x80000000
1524 #define A4XX_RB_BIN_OFFSET_X__MASK				0x00007fff
1525 #define A4XX_RB_BIN_OFFSET_X__SHIFT				0
1530 #define A4XX_RB_BIN_OFFSET_Y__MASK				0x7fff0000
1537 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }  in REG_A4XX_RB_VPORT_Z_CLAMP()
1539 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }  in REG_A4XX_RB_VPORT_Z_CLAMP_MIN()
1541 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }  in REG_A4XX_RB_VPORT_Z_CLAMP_MAX()
1543 #define REG_A4XX_RBBM_HW_VERSION				0x00000000
1545 #define REG_A4XX_RBBM_HW_CONFIGURATION				0x00000002
1547 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL_TP()
1549 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL_TP_REG()
1551 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL2_TP()
1553 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL2_TP_REG()
1555 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_HYST_TP()
1557 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_HYST_TP_REG()
1559 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_DELAY_TP()
1561 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_DELAY_TP_REG()
1563 #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 				0x00000014
1565 #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE				0x00000015
1567 #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE				0x00000016
1569 #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE				0x00000017
1571 #define REG_A4XX_RBBM_CLOCK_HYST_UCHE				0x00000018
1573 #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE				0x00000019
1575 #define REG_A4XX_RBBM_CLOCK_MODE_GPC				0x0000001a
1577 #define REG_A4XX_RBBM_CLOCK_DELAY_GPC				0x0000001b
1579 #define REG_A4XX_RBBM_CLOCK_HYST_GPC				0x0000001c
1581 #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM			0x0000001d
1583 #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM			0x0000001e
1585 #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM			0x0000001f
1587 #define REG_A4XX_RBBM_CLOCK_CTL					0x00000020
1589 #define REG_A4XX_RBBM_SP_HYST_CNT				0x00000021
1591 #define REG_A4XX_RBBM_SW_RESET_CMD				0x00000022
1593 #define REG_A4XX_RBBM_AHB_CTL0					0x00000023
1595 #define REG_A4XX_RBBM_AHB_CTL1					0x00000024
1597 #define REG_A4XX_RBBM_AHB_CMD					0x00000025
1599 #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL			0x00000026
1601 #define REG_A4XX_RBBM_RAM_ACC_63_32				0x00000028
1603 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL			0x0000002b
1605 #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL			0x0000002f
1607 #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4			0x00000034
1609 #define REG_A4XX_RBBM_INT_CLEAR_CMD				0x00000036
1611 #define REG_A4XX_RBBM_INT_0_MASK				0x00000037
1613 #define REG_A4XX_RBBM_RBBM_CTL					0x0000003e
1615 #define REG_A4XX_RBBM_AHB_DEBUG_CTL				0x0000003f
1617 #define REG_A4XX_RBBM_VBIF_DEBUG_CTL				0x00000041
1619 #define REG_A4XX_RBBM_CLOCK_CTL2				0x00000042
1621 #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD			0x00000045
1623 #define REG_A4XX_RBBM_RESET_CYCLES				0x00000047
1625 #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL				0x00000049
1627 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A				0x0000004a
1629 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B				0x0000004b
1631 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C				0x0000004c
1633 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D				0x0000004d
1635 #define REG_A4XX_RBBM_POWER_CNTL_IP				0x00000098
1636 #define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE			0x00000001
1637 #define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON			0x00100000
1639 #define REG_A4XX_RBBM_PERFCTR_CP_0_LO				0x0000009c
1641 #define REG_A4XX_RBBM_PERFCTR_CP_0_HI				0x0000009d
1643 #define REG_A4XX_RBBM_PERFCTR_CP_1_LO				0x0000009e
1645 #define REG_A4XX_RBBM_PERFCTR_CP_1_HI				0x0000009f
1647 #define REG_A4XX_RBBM_PERFCTR_CP_2_LO				0x000000a0
1649 #define REG_A4XX_RBBM_PERFCTR_CP_2_HI				0x000000a1
1651 #define REG_A4XX_RBBM_PERFCTR_CP_3_LO				0x000000a2
1653 #define REG_A4XX_RBBM_PERFCTR_CP_3_HI				0x000000a3
1655 #define REG_A4XX_RBBM_PERFCTR_CP_4_LO				0x000000a4
1657 #define REG_A4XX_RBBM_PERFCTR_CP_4_HI				0x000000a5
1659 #define REG_A4XX_RBBM_PERFCTR_CP_5_LO				0x000000a6
1661 #define REG_A4XX_RBBM_PERFCTR_CP_5_HI				0x000000a7
1663 #define REG_A4XX_RBBM_PERFCTR_CP_6_LO				0x000000a8
1665 #define REG_A4XX_RBBM_PERFCTR_CP_6_HI				0x000000a9
1667 #define REG_A4XX_RBBM_PERFCTR_CP_7_LO				0x000000aa
1669 #define REG_A4XX_RBBM_PERFCTR_CP_7_HI				0x000000ab
1671 #define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO				0x000000ac
1673 #define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI				0x000000ad
1675 #define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO				0x000000ae
1677 #define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI				0x000000af
1679 #define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO				0x000000b0
1681 #define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI				0x000000b1
1683 #define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO				0x000000b2
1685 #define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI				0x000000b3
1687 #define REG_A4XX_RBBM_PERFCTR_PC_0_LO				0x000000b4
1689 #define REG_A4XX_RBBM_PERFCTR_PC_0_HI				0x000000b5
1691 #define REG_A4XX_RBBM_PERFCTR_PC_1_LO				0x000000b6
1693 #define REG_A4XX_RBBM_PERFCTR_PC_1_HI				0x000000b7
1695 #define REG_A4XX_RBBM_PERFCTR_PC_2_LO				0x000000b8
1697 #define REG_A4XX_RBBM_PERFCTR_PC_2_HI				0x000000b9
1699 #define REG_A4XX_RBBM_PERFCTR_PC_3_LO				0x000000ba
1701 #define REG_A4XX_RBBM_PERFCTR_PC_3_HI				0x000000bb
1703 #define REG_A4XX_RBBM_PERFCTR_PC_4_LO				0x000000bc
1705 #define REG_A4XX_RBBM_PERFCTR_PC_4_HI				0x000000bd
1707 #define REG_A4XX_RBBM_PERFCTR_PC_5_LO				0x000000be
1709 #define REG_A4XX_RBBM_PERFCTR_PC_5_HI				0x000000bf
1711 #define REG_A4XX_RBBM_PERFCTR_PC_6_LO				0x000000c0
1713 #define REG_A4XX_RBBM_PERFCTR_PC_6_HI				0x000000c1
1715 #define REG_A4XX_RBBM_PERFCTR_PC_7_LO				0x000000c2
1717 #define REG_A4XX_RBBM_PERFCTR_PC_7_HI				0x000000c3
1719 #define REG_A4XX_RBBM_PERFCTR_VFD_0_LO				0x000000c4
1721 #define REG_A4XX_RBBM_PERFCTR_VFD_0_HI				0x000000c5
1723 #define REG_A4XX_RBBM_PERFCTR_VFD_1_LO				0x000000c6
1725 #define REG_A4XX_RBBM_PERFCTR_VFD_1_HI				0x000000c7
1727 #define REG_A4XX_RBBM_PERFCTR_VFD_2_LO				0x000000c8
1729 #define REG_A4XX_RBBM_PERFCTR_VFD_2_HI				0x000000c9
1731 #define REG_A4XX_RBBM_PERFCTR_VFD_3_LO				0x000000ca
1733 #define REG_A4XX_RBBM_PERFCTR_VFD_3_HI				0x000000cb
1735 #define REG_A4XX_RBBM_PERFCTR_VFD_4_LO				0x000000cc
1737 #define REG_A4XX_RBBM_PERFCTR_VFD_4_HI				0x000000cd
1739 #define REG_A4XX_RBBM_PERFCTR_VFD_5_LO				0x000000ce
1741 #define REG_A4XX_RBBM_PERFCTR_VFD_5_HI				0x000000cf
1743 #define REG_A4XX_RBBM_PERFCTR_VFD_6_LO				0x000000d0
1745 #define REG_A4XX_RBBM_PERFCTR_VFD_6_HI				0x000000d1
1747 #define REG_A4XX_RBBM_PERFCTR_VFD_7_LO				0x000000d2
1749 #define REG_A4XX_RBBM_PERFCTR_VFD_7_HI				0x000000d3
1751 #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO				0x000000d4
1753 #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI				0x000000d5
1755 #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO				0x000000d6
1757 #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI				0x000000d7
1759 #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO				0x000000d8
1761 #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI				0x000000d9
1763 #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO				0x000000da
1765 #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI				0x000000db
1767 #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO				0x000000dc
1769 #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI				0x000000dd
1771 #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO				0x000000de
1773 #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI				0x000000df
1775 #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO				0x000000e0
1777 #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI				0x000000e1
1779 #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO				0x000000e2
1781 #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI				0x000000e3
1783 #define REG_A4XX_RBBM_PERFCTR_VPC_0_LO				0x000000e4
1785 #define REG_A4XX_RBBM_PERFCTR_VPC_0_HI				0x000000e5
1787 #define REG_A4XX_RBBM_PERFCTR_VPC_1_LO				0x000000e6
1789 #define REG_A4XX_RBBM_PERFCTR_VPC_1_HI				0x000000e7
1791 #define REG_A4XX_RBBM_PERFCTR_VPC_2_LO				0x000000e8
1793 #define REG_A4XX_RBBM_PERFCTR_VPC_2_HI				0x000000e9
1795 #define REG_A4XX_RBBM_PERFCTR_VPC_3_LO				0x000000ea
1797 #define REG_A4XX_RBBM_PERFCTR_VPC_3_HI				0x000000eb
1799 #define REG_A4XX_RBBM_PERFCTR_CCU_0_LO				0x000000ec
1801 #define REG_A4XX_RBBM_PERFCTR_CCU_0_HI				0x000000ed
1803 #define REG_A4XX_RBBM_PERFCTR_CCU_1_LO				0x000000ee
1805 #define REG_A4XX_RBBM_PERFCTR_CCU_1_HI				0x000000ef
1807 #define REG_A4XX_RBBM_PERFCTR_CCU_2_LO				0x000000f0
1809 #define REG_A4XX_RBBM_PERFCTR_CCU_2_HI				0x000000f1
1811 #define REG_A4XX_RBBM_PERFCTR_CCU_3_LO				0x000000f2
1813 #define REG_A4XX_RBBM_PERFCTR_CCU_3_HI				0x000000f3
1815 #define REG_A4XX_RBBM_PERFCTR_TSE_0_LO				0x000000f4
1817 #define REG_A4XX_RBBM_PERFCTR_TSE_0_HI				0x000000f5
1819 #define REG_A4XX_RBBM_PERFCTR_TSE_1_LO				0x000000f6
1821 #define REG_A4XX_RBBM_PERFCTR_TSE_1_HI				0x000000f7
1823 #define REG_A4XX_RBBM_PERFCTR_TSE_2_LO				0x000000f8
1825 #define REG_A4XX_RBBM_PERFCTR_TSE_2_HI				0x000000f9
1827 #define REG_A4XX_RBBM_PERFCTR_TSE_3_LO				0x000000fa
1829 #define REG_A4XX_RBBM_PERFCTR_TSE_3_HI				0x000000fb
1831 #define REG_A4XX_RBBM_PERFCTR_RAS_0_LO				0x000000fc
1833 #define REG_A4XX_RBBM_PERFCTR_RAS_0_HI				0x000000fd
1835 #define REG_A4XX_RBBM_PERFCTR_RAS_1_LO				0x000000fe
1837 #define REG_A4XX_RBBM_PERFCTR_RAS_1_HI				0x000000ff
1839 #define REG_A4XX_RBBM_PERFCTR_RAS_2_LO				0x00000100
1841 #define REG_A4XX_RBBM_PERFCTR_RAS_2_HI				0x00000101
1843 #define REG_A4XX_RBBM_PERFCTR_RAS_3_LO				0x00000102
1845 #define REG_A4XX_RBBM_PERFCTR_RAS_3_HI				0x00000103
1847 #define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO				0x00000104
1849 #define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI				0x00000105
1851 #define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO				0x00000106
1853 #define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI				0x00000107
1855 #define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO				0x00000108
1857 #define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI				0x00000109
1859 #define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO				0x0000010a
1861 #define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI				0x0000010b
1863 #define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO				0x0000010c
1865 #define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI				0x0000010d
1867 #define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO				0x0000010e
1869 #define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI				0x0000010f
1871 #define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO				0x00000110
1873 #define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI				0x00000111
1875 #define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO				0x00000112
1877 #define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI				0x00000113
1879 #define REG_A4XX_RBBM_PERFCTR_TP_0_LO				0x00000114
1881 #define REG_A4XX_RBBM_PERFCTR_TP_0_HI				0x00000115
1883 #define REG_A4XX_RBBM_PERFCTR_TP_1_LO				0x00000116
1885 #define REG_A4XX_RBBM_PERFCTR_TP_1_HI				0x00000117
1887 #define REG_A4XX_RBBM_PERFCTR_TP_2_LO				0x00000118
1889 #define REG_A4XX_RBBM_PERFCTR_TP_2_HI				0x00000119
1891 #define REG_A4XX_RBBM_PERFCTR_TP_3_LO				0x0000011a
1893 #define REG_A4XX_RBBM_PERFCTR_TP_3_HI				0x0000011b
1895 #define REG_A4XX_RBBM_PERFCTR_TP_4_LO				0x0000011c
1897 #define REG_A4XX_RBBM_PERFCTR_TP_4_HI				0x0000011d
1899 #define REG_A4XX_RBBM_PERFCTR_TP_5_LO				0x0000011e
1901 #define REG_A4XX_RBBM_PERFCTR_TP_5_HI				0x0000011f
1903 #define REG_A4XX_RBBM_PERFCTR_TP_6_LO				0x00000120
1905 #define REG_A4XX_RBBM_PERFCTR_TP_6_HI				0x00000121
1907 #define REG_A4XX_RBBM_PERFCTR_TP_7_LO				0x00000122
1909 #define REG_A4XX_RBBM_PERFCTR_TP_7_HI				0x00000123
1911 #define REG_A4XX_RBBM_PERFCTR_SP_0_LO				0x00000124
1913 #define REG_A4XX_RBBM_PERFCTR_SP_0_HI				0x00000125
1915 #define REG_A4XX_RBBM_PERFCTR_SP_1_LO				0x00000126
1917 #define REG_A4XX_RBBM_PERFCTR_SP_1_HI				0x00000127
1919 #define REG_A4XX_RBBM_PERFCTR_SP_2_LO				0x00000128
1921 #define REG_A4XX_RBBM_PERFCTR_SP_2_HI				0x00000129
1923 #define REG_A4XX_RBBM_PERFCTR_SP_3_LO				0x0000012a
1925 #define REG_A4XX_RBBM_PERFCTR_SP_3_HI				0x0000012b
1927 #define REG_A4XX_RBBM_PERFCTR_SP_4_LO				0x0000012c
1929 #define REG_A4XX_RBBM_PERFCTR_SP_4_HI				0x0000012d
1931 #define REG_A4XX_RBBM_PERFCTR_SP_5_LO				0x0000012e
1933 #define REG_A4XX_RBBM_PERFCTR_SP_5_HI				0x0000012f
1935 #define REG_A4XX_RBBM_PERFCTR_SP_6_LO				0x00000130
1937 #define REG_A4XX_RBBM_PERFCTR_SP_6_HI				0x00000131
1939 #define REG_A4XX_RBBM_PERFCTR_SP_7_LO				0x00000132
1941 #define REG_A4XX_RBBM_PERFCTR_SP_7_HI				0x00000133
1943 #define REG_A4XX_RBBM_PERFCTR_SP_8_LO				0x00000134
1945 #define REG_A4XX_RBBM_PERFCTR_SP_8_HI				0x00000135
1947 #define REG_A4XX_RBBM_PERFCTR_SP_9_LO				0x00000136
1949 #define REG_A4XX_RBBM_PERFCTR_SP_9_HI				0x00000137
1951 #define REG_A4XX_RBBM_PERFCTR_SP_10_LO				0x00000138
1953 #define REG_A4XX_RBBM_PERFCTR_SP_10_HI				0x00000139
1955 #define REG_A4XX_RBBM_PERFCTR_SP_11_LO				0x0000013a
1957 #define REG_A4XX_RBBM_PERFCTR_SP_11_HI				0x0000013b
1959 #define REG_A4XX_RBBM_PERFCTR_RB_0_LO				0x0000013c
1961 #define REG_A4XX_RBBM_PERFCTR_RB_0_HI				0x0000013d
1963 #define REG_A4XX_RBBM_PERFCTR_RB_1_LO				0x0000013e
1965 #define REG_A4XX_RBBM_PERFCTR_RB_1_HI				0x0000013f
1967 #define REG_A4XX_RBBM_PERFCTR_RB_2_LO				0x00000140
1969 #define REG_A4XX_RBBM_PERFCTR_RB_2_HI				0x00000141
1971 #define REG_A4XX_RBBM_PERFCTR_RB_3_LO				0x00000142
1973 #define REG_A4XX_RBBM_PERFCTR_RB_3_HI				0x00000143
1975 #define REG_A4XX_RBBM_PERFCTR_RB_4_LO				0x00000144
1977 #define REG_A4XX_RBBM_PERFCTR_RB_4_HI				0x00000145
1979 #define REG_A4XX_RBBM_PERFCTR_RB_5_LO				0x00000146
1981 #define REG_A4XX_RBBM_PERFCTR_RB_5_HI				0x00000147
1983 #define REG_A4XX_RBBM_PERFCTR_RB_6_LO				0x00000148
1985 #define REG_A4XX_RBBM_PERFCTR_RB_6_HI				0x00000149
1987 #define REG_A4XX_RBBM_PERFCTR_RB_7_LO				0x0000014a
1989 #define REG_A4XX_RBBM_PERFCTR_RB_7_HI				0x0000014b
1991 #define REG_A4XX_RBBM_PERFCTR_VSC_0_LO				0x0000014c
1993 #define REG_A4XX_RBBM_PERFCTR_VSC_0_HI				0x0000014d
1995 #define REG_A4XX_RBBM_PERFCTR_VSC_1_LO				0x0000014e
1997 #define REG_A4XX_RBBM_PERFCTR_VSC_1_HI				0x0000014f
1999 #define REG_A4XX_RBBM_PERFCTR_PWR_0_LO				0x00000166
2001 #define REG_A4XX_RBBM_PERFCTR_PWR_0_HI				0x00000167
2003 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO				0x00000168
2005 #define REG_A4XX_RBBM_PERFCTR_PWR_1_HI				0x00000169
2007 #define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO			0x0000016e
2009 #define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI			0x0000016f
2011 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL_SP()
2013 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL_SP_REG()
2015 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL2_SP()
2017 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL2_SP_REG()
2019 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_HYST_SP()
2021 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_HYST_SP_REG()
2023 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_DELAY_SP()
2025 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_DELAY_SP_REG()
2027 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL_RB()
2029 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL_RB_REG()
2031 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL2_RB()
2033 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL2_RB_REG()
2035 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU()
2037 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*…  in REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG()
2039 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*…  in REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU()
2041 …line uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG()
2043 #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM			0x00000080
2045 #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM			0x00000081
2047 #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ				0x0000008a
2049 #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ				0x0000008b
2051 #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ				0x0000008c
2053 #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM			0x0000008d
2055 …line uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1()
2057 … uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }  in REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG()
2059 #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0			0x00000099
2061 #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1			0x0000009a
2063 #define REG_A4XX_RBBM_PERFCTR_CTL				0x00000170
2065 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0				0x00000171
2067 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1				0x00000172
2069 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2				0x00000173
2071 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO			0x00000174
2073 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI			0x00000175
2075 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0			0x00000176
2077 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1			0x00000177
2079 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2			0x00000178
2081 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3			0x00000179
2083 #define REG_A4XX_RBBM_GPU_BUSY_MASKED				0x0000017a
2085 #define REG_A4XX_RBBM_INT_0_STATUS				0x0000017d
2087 #define REG_A4XX_RBBM_CLOCK_STATUS				0x00000182
2089 #define REG_A4XX_RBBM_AHB_STATUS				0x00000189
2091 #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS			0x0000018c
2093 #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS			0x0000018d
2095 #define REG_A4XX_RBBM_AHB_ERROR_STATUS				0x0000018f
2097 #define REG_A4XX_RBBM_STATUS					0x00000191
2098 #define A4XX_RBBM_STATUS_HI_BUSY				0x00000001
2099 #define A4XX_RBBM_STATUS_CP_ME_BUSY				0x00000002
2100 #define A4XX_RBBM_STATUS_CP_PFP_BUSY				0x00000004
2101 #define A4XX_RBBM_STATUS_CP_NRT_BUSY				0x00004000
2102 #define A4XX_RBBM_STATUS_VBIF_BUSY				0x00008000
2103 #define A4XX_RBBM_STATUS_TSE_BUSY				0x00010000
2104 #define A4XX_RBBM_STATUS_RAS_BUSY				0x00020000
2105 #define A4XX_RBBM_STATUS_RB_BUSY				0x00040000
2106 #define A4XX_RBBM_STATUS_PC_DCALL_BUSY				0x00080000
2107 #define A4XX_RBBM_STATUS_PC_VSD_BUSY				0x00100000
2108 #define A4XX_RBBM_STATUS_VFD_BUSY				0x00200000
2109 #define A4XX_RBBM_STATUS_VPC_BUSY				0x00400000
2110 #define A4XX_RBBM_STATUS_UCHE_BUSY				0x00800000
2111 #define A4XX_RBBM_STATUS_SP_BUSY				0x01000000
2112 #define A4XX_RBBM_STATUS_TPL1_BUSY				0x02000000
2113 #define A4XX_RBBM_STATUS_MARB_BUSY				0x04000000
2114 #define A4XX_RBBM_STATUS_VSC_BUSY				0x08000000
2115 #define A4XX_RBBM_STATUS_ARB_BUSY				0x10000000
2116 #define A4XX_RBBM_STATUS_HLSQ_BUSY				0x20000000
2117 #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC				0x40000000
2118 #define A4XX_RBBM_STATUS_GPU_BUSY				0x80000000
2120 #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5			0x0000019f
2122 #define REG_A4XX_RBBM_POWER_STATUS				0x000001b0
2123 #define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON			0x00100000
2125 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2			0x000001b8
2127 #define REG_A4XX_CP_SCRATCH_UMASK				0x00000228
2129 #define REG_A4XX_CP_SCRATCH_ADDR				0x00000229
2131 #define REG_A4XX_CP_RB_BASE					0x00000200
2133 #define REG_A4XX_CP_RB_CNTL					0x00000201
2135 #define REG_A4XX_CP_RB_WPTR					0x00000205
2137 #define REG_A4XX_CP_RB_RPTR_ADDR				0x00000203
2139 #define REG_A4XX_CP_RB_RPTR					0x00000204
2141 #define REG_A4XX_CP_IB1_BASE					0x00000206
2143 #define REG_A4XX_CP_IB1_BUFSZ					0x00000207
2145 #define REG_A4XX_CP_IB2_BASE					0x00000208
2147 #define REG_A4XX_CP_IB2_BUFSZ					0x00000209
2149 #define REG_A4XX_CP_ME_NRT_ADDR					0x0000020c
2151 #define REG_A4XX_CP_ME_NRT_DATA					0x0000020d
2153 #define REG_A4XX_CP_ME_RB_DONE_DATA				0x00000217
2155 #define REG_A4XX_CP_QUEUE_THRESH2				0x00000219
2157 #define REG_A4XX_CP_MERCIU_SIZE					0x0000021b
2159 #define REG_A4XX_CP_ROQ_ADDR					0x0000021c
2161 #define REG_A4XX_CP_ROQ_DATA					0x0000021d
2163 #define REG_A4XX_CP_MEQ_ADDR					0x0000021e
2165 #define REG_A4XX_CP_MEQ_DATA					0x0000021f
2167 #define REG_A4XX_CP_MERCIU_ADDR					0x00000220
2169 #define REG_A4XX_CP_MERCIU_DATA					0x00000221
2171 #define REG_A4XX_CP_MERCIU_DATA2				0x00000222
2173 #define REG_A4XX_CP_PFP_UCODE_ADDR				0x00000223
2175 #define REG_A4XX_CP_PFP_UCODE_DATA				0x00000224
2177 #define REG_A4XX_CP_ME_RAM_WADDR				0x00000225
2179 #define REG_A4XX_CP_ME_RAM_RADDR				0x00000226
2181 #define REG_A4XX_CP_ME_RAM_DATA					0x00000227
2183 #define REG_A4XX_CP_PREEMPT					0x0000022a
2185 #define REG_A4XX_CP_CNTL					0x0000022c
2187 #define REG_A4XX_CP_ME_CNTL					0x0000022d
2189 #define REG_A4XX_CP_DEBUG					0x0000022e
2191 #define REG_A4XX_CP_DEBUG_ECO_CONTROL				0x00000231
2193 #define REG_A4XX_CP_DRAW_STATE_ADDR				0x00000232
2195 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }  in REG_A4XX_CP_PROTECT()
2197 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }  in REG_A4XX_CP_PROTECT_REG()
2198 #define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK			0x0001ffff
2199 #define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT			0
2204 #define A4XX_CP_PROTECT_REG_MASK_LEN__MASK			0x1f000000
2210 #define A4XX_CP_PROTECT_REG_TRAP_WRITE__MASK			0x20000000
2216 #define A4XX_CP_PROTECT_REG_TRAP_READ__MASK			0x40000000
2223 #define REG_A4XX_CP_PROTECT_CTRL				0x00000250
2225 #define REG_A4XX_CP_ST_BASE					0x000004c0
2227 #define REG_A4XX_CP_STQ_AVAIL					0x000004ce
2229 #define REG_A4XX_CP_MERCIU_STAT					0x000004d0
2231 #define REG_A4XX_CP_WFI_PEND_CTR				0x000004d2
2233 #define REG_A4XX_CP_HW_FAULT					0x000004d8
2235 #define REG_A4XX_CP_PROTECT_STATUS				0x000004da
2237 #define REG_A4XX_CP_EVENTS_IN_FLIGHT				0x000004dd
2239 #define REG_A4XX_CP_PERFCTR_CP_SEL_0				0x00000500
2241 #define REG_A4XX_CP_PERFCTR_CP_SEL_1				0x00000501
2243 #define REG_A4XX_CP_PERFCTR_CP_SEL_2				0x00000502
2245 #define REG_A4XX_CP_PERFCTR_CP_SEL_3				0x00000503
2247 #define REG_A4XX_CP_PERFCTR_CP_SEL_4				0x00000504
2249 #define REG_A4XX_CP_PERFCTR_CP_SEL_5				0x00000505
2251 #define REG_A4XX_CP_PERFCTR_CP_SEL_6				0x00000506
2253 #define REG_A4XX_CP_PERFCTR_CP_SEL_7				0x00000507
2255 #define REG_A4XX_CP_PERFCOMBINER_SELECT				0x0000050b
2257 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }  in REG_A4XX_CP_SCRATCH()
2259 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }  in REG_A4XX_CP_SCRATCH_REG()
2261 #define REG_A4XX_SP_VS_STATUS					0x00000ec0
2263 #define REG_A4XX_SP_MODE_CONTROL				0x00000ec3
2265 #define REG_A4XX_SP_PERFCTR_SP_SEL_0				0x00000ec4
2267 #define REG_A4XX_SP_PERFCTR_SP_SEL_1				0x00000ec5
2269 #define REG_A4XX_SP_PERFCTR_SP_SEL_2				0x00000ec6
2271 #define REG_A4XX_SP_PERFCTR_SP_SEL_3				0x00000ec7
2273 #define REG_A4XX_SP_PERFCTR_SP_SEL_4				0x00000ec8
2275 #define REG_A4XX_SP_PERFCTR_SP_SEL_5				0x00000ec9
2277 #define REG_A4XX_SP_PERFCTR_SP_SEL_6				0x00000eca
2279 #define REG_A4XX_SP_PERFCTR_SP_SEL_7				0x00000ecb
2281 #define REG_A4XX_SP_PERFCTR_SP_SEL_8				0x00000ecc
2283 #define REG_A4XX_SP_PERFCTR_SP_SEL_9				0x00000ecd
2285 #define REG_A4XX_SP_PERFCTR_SP_SEL_10				0x00000ece
2287 #define REG_A4XX_SP_PERFCTR_SP_SEL_11				0x00000ecf
2289 #define REG_A4XX_SP_SP_CTRL_REG					0x000022c0
2290 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS			0x00080000
2292 #define REG_A4XX_SP_INSTR_CACHE_CTRL				0x000022c1
2293 #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER			0x00000080
2294 #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER			0x00000100
2295 #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER			0x00000400
2297 #define REG_A4XX_SP_VS_CTRL_REG0				0x000022c4
2298 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK			0x00000001
2299 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT			0
2304 #define A4XX_SP_VS_CTRL_REG0_VARYING				0x00000002
2305 #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID			0x00000004
2306 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
2312 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
2318 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK		0x000c0000
2324 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK			0x00100000
2330 #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE			0x00200000
2331 #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE			0x00400000
2333 #define REG_A4XX_SP_VS_CTRL_REG1				0x000022c5
2334 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK			0x000000ff
2335 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT			0
2340 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK		0x7f000000
2347 #define REG_A4XX_SP_VS_PARAM_REG				0x000022c6
2348 #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK			0x000000ff
2349 #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT			0
2354 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK			0x0000ff00
2360 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK		0xfff00000
2367 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }  in REG_A4XX_SP_VS_OUT()
2369 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }  in REG_A4XX_SP_VS_OUT_REG()
2370 #define A4XX_SP_VS_OUT_REG_A_REGID__MASK			0x000001ff
2371 #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT			0
2376 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK			0x00001e00
2382 #define A4XX_SP_VS_OUT_REG_B_REGID__MASK			0x01ff0000
2388 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK			0x1e000000
2395 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }  in REG_A4XX_SP_VS_VPC_DST()
2397 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }  in REG_A4XX_SP_VS_VPC_DST_REG()
2398 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
2399 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT			0
2404 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
2410 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
2416 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
2423 #define REG_A4XX_SP_VS_OBJ_OFFSET_REG				0x000022e0
2424 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK	0x01ff0000
2430 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK		0xfe000000
2437 #define REG_A4XX_SP_VS_OBJ_START				0x000022e1
2439 #define REG_A4XX_SP_VS_PVT_MEM_PARAM				0x000022e2
2441 #define REG_A4XX_SP_VS_PVT_MEM_ADDR				0x000022e3
2443 #define REG_A4XX_SP_VS_LENGTH_REG				0x000022e5
2445 #define REG_A4XX_SP_FS_CTRL_REG0				0x000022e8
2446 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK			0x00000001
2447 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT			0
2452 #define A4XX_SP_FS_CTRL_REG0_VARYING				0x00000002
2453 #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID			0x00000004
2454 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
2460 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
2466 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK		0x000c0000
2472 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK			0x00100000
2478 #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE			0x00200000
2479 #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE			0x00400000
2481 #define REG_A4XX_SP_FS_CTRL_REG1				0x000022e9
2482 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK			0x000000ff
2483 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT			0
2488 #define A4XX_SP_FS_CTRL_REG1_FACENESS				0x00080000
2489 #define A4XX_SP_FS_CTRL_REG1_VARYING				0x00100000
2490 #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD				0x00200000
2492 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG				0x000022ea
2493 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK	0x01ff0000
2499 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK		0xfe000000
2506 #define REG_A4XX_SP_FS_OBJ_START				0x000022eb
2508 #define REG_A4XX_SP_FS_PVT_MEM_PARAM				0x000022ec
2510 #define REG_A4XX_SP_FS_PVT_MEM_ADDR				0x000022ed
2512 #define REG_A4XX_SP_FS_LENGTH_REG				0x000022ef
2514 #define REG_A4XX_SP_FS_OUTPUT_REG				0x000022f0
2515 #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK				0x0000000f
2516 #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT			0
2521 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE			0x00000080
2522 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK			0x0000ff00
2528 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK		0xff000000
2535 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }  in REG_A4XX_SP_FS_MRT()
2537 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }  in REG_A4XX_SP_FS_MRT_REG()
2538 #define A4XX_SP_FS_MRT_REG_REGID__MASK				0x000000ff
2539 #define A4XX_SP_FS_MRT_REG_REGID__SHIFT				0
2544 #define A4XX_SP_FS_MRT_REG_HALF_PRECISION			0x00000100
2545 #define A4XX_SP_FS_MRT_REG_COLOR_SINT				0x00000400
2546 #define A4XX_SP_FS_MRT_REG_COLOR_UINT				0x00000800
2547 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK			0x0003f000
2553 #define A4XX_SP_FS_MRT_REG_COLOR_SRGB				0x00040000
2555 #define REG_A4XX_SP_CS_CTRL_REG0				0x00002300
2556 #define A4XX_SP_CS_CTRL_REG0_THREADMODE__MASK			0x00000001
2557 #define A4XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT			0
2562 #define A4XX_SP_CS_CTRL_REG0_VARYING				0x00000002
2563 #define A4XX_SP_CS_CTRL_REG0_CACHEINVALID			0x00000004
2564 #define A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
2570 #define A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
2576 #define A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__MASK		0x000c0000
2582 #define A4XX_SP_CS_CTRL_REG0_THREADSIZE__MASK			0x00100000
2588 #define A4XX_SP_CS_CTRL_REG0_SUPERTHREADMODE			0x00200000
2589 #define A4XX_SP_CS_CTRL_REG0_PIXLODENABLE			0x00400000
2591 #define REG_A4XX_SP_CS_OBJ_OFFSET_REG				0x00002301
2593 #define REG_A4XX_SP_CS_OBJ_START				0x00002302
2595 #define REG_A4XX_SP_CS_PVT_MEM_PARAM				0x00002303
2597 #define REG_A4XX_SP_CS_PVT_MEM_ADDR				0x00002304
2599 #define REG_A4XX_SP_CS_PVT_MEM_SIZE				0x00002305
2601 #define REG_A4XX_SP_CS_LENGTH_REG				0x00002306
2603 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG				0x0000230d
2604 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK	0x01ff0000
2610 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK		0xfe000000
2617 #define REG_A4XX_SP_HS_OBJ_START				0x0000230e
2619 #define REG_A4XX_SP_HS_PVT_MEM_PARAM				0x0000230f
2621 #define REG_A4XX_SP_HS_PVT_MEM_ADDR				0x00002310
2623 #define REG_A4XX_SP_HS_LENGTH_REG				0x00002312
2625 #define REG_A4XX_SP_DS_PARAM_REG				0x0000231a
2626 #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK			0x000000ff
2627 #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT			0
2632 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK		0xfff00000
2639 static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }  in REG_A4XX_SP_DS_OUT()
2641 static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }  in REG_A4XX_SP_DS_OUT_REG()
2642 #define A4XX_SP_DS_OUT_REG_A_REGID__MASK			0x000001ff
2643 #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT			0
2648 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK			0x00001e00
2654 #define A4XX_SP_DS_OUT_REG_B_REGID__MASK			0x01ff0000
2660 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK			0x1e000000
2667 static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }  in REG_A4XX_SP_DS_VPC_DST()
2669 static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }  in REG_A4XX_SP_DS_VPC_DST_REG()
2670 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
2671 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT			0
2676 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
2682 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
2688 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
2695 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG				0x00002334
2696 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK	0x01ff0000
2702 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK		0xfe000000
2709 #define REG_A4XX_SP_DS_OBJ_START				0x00002335
2711 #define REG_A4XX_SP_DS_PVT_MEM_PARAM				0x00002336
2713 #define REG_A4XX_SP_DS_PVT_MEM_ADDR				0x00002337
2715 #define REG_A4XX_SP_DS_LENGTH_REG				0x00002339
2717 #define REG_A4XX_SP_GS_PARAM_REG				0x00002341
2718 #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK			0x000000ff
2719 #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT			0
2724 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK			0x0000ff00
2730 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK		0xfff00000
2737 static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }  in REG_A4XX_SP_GS_OUT()
2739 static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }  in REG_A4XX_SP_GS_OUT_REG()
2740 #define A4XX_SP_GS_OUT_REG_A_REGID__MASK			0x000001ff
2741 #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT			0
2746 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK			0x00001e00
2752 #define A4XX_SP_GS_OUT_REG_B_REGID__MASK			0x01ff0000
2758 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK			0x1e000000
2765 static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }  in REG_A4XX_SP_GS_VPC_DST()
2767 static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }  in REG_A4XX_SP_GS_VPC_DST_REG()
2768 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
2769 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT			0
2774 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
2780 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
2786 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
2793 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG				0x0000235b
2794 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK	0x01ff0000
2800 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK		0xfe000000
2807 #define REG_A4XX_SP_GS_OBJ_START				0x0000235c
2809 #define REG_A4XX_SP_GS_PVT_MEM_PARAM				0x0000235d
2811 #define REG_A4XX_SP_GS_PVT_MEM_ADDR				0x0000235e
2813 #define REG_A4XX_SP_GS_LENGTH_REG				0x00002360
2815 #define REG_A4XX_VPC_DEBUG_RAM_SEL				0x00000e60
2817 #define REG_A4XX_VPC_DEBUG_RAM_READ				0x00000e61
2819 #define REG_A4XX_VPC_DEBUG_ECO_CONTROL				0x00000e64
2821 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_0				0x00000e65
2823 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_1				0x00000e66
2825 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_2				0x00000e67
2827 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3				0x00000e68
2829 #define REG_A4XX_VPC_ATTR					0x00002140
2830 #define A4XX_VPC_ATTR_TOTALATTR__MASK				0x000001ff
2831 #define A4XX_VPC_ATTR_TOTALATTR__SHIFT				0
2836 #define A4XX_VPC_ATTR_PSIZE					0x00000200
2837 #define A4XX_VPC_ATTR_THRDASSIGN__MASK				0x00003000
2843 #define A4XX_VPC_ATTR_ENABLE					0x02000000
2845 #define REG_A4XX_VPC_PACK					0x00002141
2846 #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK			0x000000ff
2847 #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT			0
2852 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK			0x0000ff00
2858 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK			0x00ff0000
2865 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }  in REG_A4XX_VPC_VARYING_INTERP()
2867 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }  in REG_A4XX_VPC_VARYING_INTERP_MODE()
2869 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }  in REG_A4XX_VPC_VARYING_PS_REPL()
2871 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0;…  in REG_A4XX_VPC_VARYING_PS_REPL_MODE()
2873 #define REG_A4XX_VPC_SO_FLUSH_WADDR_3				0x0000216e
2875 #define REG_A4XX_VSC_BIN_SIZE					0x00000c00
2876 #define A4XX_VSC_BIN_SIZE_WIDTH__MASK				0x0000001f
2877 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT				0
2882 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK				0x000003e0
2889 #define REG_A4XX_VSC_SIZE_ADDRESS				0x00000c01
2891 #define REG_A4XX_VSC_SIZE_ADDRESS2				0x00000c02
2893 #define REG_A4XX_VSC_DEBUG_ECO_CONTROL				0x00000c03
2895 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }  in REG_A4XX_VSC_PIPE_CONFIG()
2897 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }  in REG_A4XX_VSC_PIPE_CONFIG_REG()
2898 #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK			0x000003ff
2899 #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT			0
2904 #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK			0x000ffc00
2910 #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK			0x00f00000
2916 #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK			0x0f000000
2923 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }  in REG_A4XX_VSC_PIPE_DATA_ADDRESS()
2925 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0…  in REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG()
2927 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }  in REG_A4XX_VSC_PIPE_DATA_LENGTH()
2929 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0;…  in REG_A4XX_VSC_PIPE_DATA_LENGTH_REG()
2931 #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1			0x00000c41
2933 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0				0x00000c50
2935 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1				0x00000c51
2937 #define REG_A4XX_VFD_DEBUG_CONTROL				0x00000e40
2939 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_0				0x00000e43
2941 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_1				0x00000e44
2943 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_2				0x00000e45
2945 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_3				0x00000e46
2947 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_4				0x00000e47
2949 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_5				0x00000e48
2951 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_6				0x00000e49
2953 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7				0x00000e4a
2955 #define REG_A4XX_VGT_CL_INITIATOR				0x000021d0
2957 #define REG_A4XX_VGT_EVENT_INITIATOR				0x000021d9
2959 #define REG_A4XX_VFD_CONTROL_0					0x00002200
2960 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK			0x000000ff
2961 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT			0
2966 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK			0x0001fe00
2972 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK		0x03f00000
2978 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK		0xfc000000
2985 #define REG_A4XX_VFD_CONTROL_1					0x00002201
2986 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK			0x0000ffff
2987 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT			0
2992 #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK			0x00ff0000
2998 #define A4XX_VFD_CONTROL_1_REGID4INST__MASK			0xff000000
3005 #define REG_A4XX_VFD_CONTROL_2					0x00002202
3007 #define REG_A4XX_VFD_CONTROL_3					0x00002203
3008 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK			0x0000ff00
3014 #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK			0x00ff0000
3020 #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK			0xff000000
3027 #define REG_A4XX_VFD_CONTROL_4					0x00002204
3029 #define REG_A4XX_VFD_INDEX_OFFSET				0x00002208
3031 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }  in REG_A4XX_VFD_FETCH()
3033 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }  in REG_A4XX_VFD_FETCH_INSTR_0()
3034 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK			0x0000007f
3035 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT			0
3040 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK			0x0001ff80
3046 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT			0x00080000
3047 #define A4XX_VFD_FETCH_INSTR_0_INSTANCED			0x00100000
3049 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }  in REG_A4XX_VFD_FETCH_INSTR_1()
3051 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }  in REG_A4XX_VFD_FETCH_INSTR_2()
3052 #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK			0xffffffff
3053 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT			0
3059 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }  in REG_A4XX_VFD_FETCH_INSTR_3()
3060 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK			0x000001ff
3061 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT			0
3067 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }  in REG_A4XX_VFD_DECODE()
3069 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }  in REG_A4XX_VFD_DECODE_INSTR()
3070 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK			0x0000000f
3071 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT			0
3076 #define A4XX_VFD_DECODE_INSTR_CONSTFILL				0x00000010
3077 #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK			0x00000fc0
3083 #define A4XX_VFD_DECODE_INSTR_REGID__MASK			0x000ff000
3089 #define A4XX_VFD_DECODE_INSTR_INT				0x00100000
3090 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK			0x00c00000
3096 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK			0x1f000000
3102 #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID			0x20000000
3103 #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT			0x40000000
3105 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL				0x00000f00
3107 #define REG_A4XX_TPL1_TP_MODE_CONTROL				0x00000f03
3109 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_0				0x00000f04
3111 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_1				0x00000f05
3113 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_2				0x00000f06
3115 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_3				0x00000f07
3117 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_4				0x00000f08
3119 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_5				0x00000f09
3121 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_6				0x00000f0a
3123 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7				0x00000f0b
3125 #define REG_A4XX_TPL1_TP_TEX_OFFSET				0x00002380
3127 #define REG_A4XX_TPL1_TP_TEX_COUNT				0x00002381
3128 #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK				0x000000ff
3129 #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT			0
3134 #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK				0x0000ff00
3140 #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK				0x00ff0000
3146 #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK				0xff000000
3153 #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR		0x00002384
3155 #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR		0x00002387
3157 #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR		0x0000238a
3159 #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR		0x0000238d
3161 #define REG_A4XX_TPL1_TP_FS_TEX_COUNT				0x000023a0
3162 #define A4XX_TPL1_TP_FS_TEX_COUNT_FS__MASK			0x000000ff
3163 #define A4XX_TPL1_TP_FS_TEX_COUNT_FS__SHIFT			0
3168 #define A4XX_TPL1_TP_FS_TEX_COUNT_CS__MASK			0x0000ff00
3175 #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR		0x000023a1
3177 #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR		0x000023a4
3179 #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR			0x000023a5
3181 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR			0x000023a6
3183 #define REG_A4XX_GRAS_TSE_STATUS				0x00000c80
3185 #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL				0x00000c81
3187 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0				0x00000c88
3189 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1				0x00000c89
3191 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2				0x00000c8a
3193 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3				0x00000c8b
3195 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0				0x00000c8c
3197 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1				0x00000c8d
3199 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2				0x00000c8e
3201 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3				0x00000c8f
3203 #define REG_A4XX_GRAS_CL_CLIP_CNTL				0x00002000
3204 #define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE			0x00008000
3205 #define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE		0x00010000
3206 #define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE		0x00020000
3207 #define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z			0x00400000
3209 #define REG_A4XX_GRAS_CNTL					0x00002003
3210 #define A4XX_GRAS_CNTL_IJ_PERSP					0x00000001
3211 #define A4XX_GRAS_CNTL_IJ_LINEAR				0x00000002
3213 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ				0x00002004
3214 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK			0x000003ff
3215 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT			0
3220 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK			0x000ffc00
3227 #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0			0x00002008
3228 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK			0xffffffff
3229 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT			0
3235 #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0				0x00002009
3236 #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK			0xffffffff
3237 #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT			0
3243 #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0			0x0000200a
3244 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK			0xffffffff
3245 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT			0
3251 #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0				0x0000200b
3252 #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK			0xffffffff
3253 #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT			0
3259 #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0			0x0000200c
3260 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK			0xffffffff
3261 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT			0
3267 #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0				0x0000200d
3268 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK			0xffffffff
3269 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT			0
3275 #define REG_A4XX_GRAS_SU_POINT_MINMAX				0x00002070
3276 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK			0x0000ffff
3277 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT			0
3282 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK			0xffff0000
3289 #define REG_A4XX_GRAS_SU_POINT_SIZE				0x00002071
3290 #define A4XX_GRAS_SU_POINT_SIZE__MASK				0xffffffff
3291 #define A4XX_GRAS_SU_POINT_SIZE__SHIFT				0
3297 #define REG_A4XX_GRAS_ALPHA_CONTROL				0x00002073
3298 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE		0x00000004
3299 #define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS		0x00000008
3301 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE			0x00002074
3302 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK			0xffffffff
3303 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT			0
3309 #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET			0x00002075
3310 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK			0xffffffff
3311 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT			0
3317 #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP			0x00002076
3318 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK			0xffffffff
3319 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT			0
3325 #define REG_A4XX_GRAS_DEPTH_CONTROL				0x00002077
3326 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK			0x00000003
3327 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT			0
3333 #define REG_A4XX_GRAS_SU_MODE_CONTROL				0x00002078
3334 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT			0x00000001
3335 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK			0x00000002
3336 #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW			0x00000004
3337 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK		0x000007f8
3343 #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET			0x00000800
3344 #define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE			0x00002000
3345 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS		0x00100000
3347 #define REG_A4XX_GRAS_SC_CONTROL				0x0000207b
3348 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK			0x0000000c
3354 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK			0x00000380
3360 #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE			0x00000800
3361 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK			0x0000f000
3368 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL			0x0000207c
3369 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE	0x80000000
3370 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK			0x00007fff
3371 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT			0
3376 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK			0x7fff0000
3383 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR			0x0000207d
3384 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE	0x80000000
3385 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK			0x00007fff
3386 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT			0
3391 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK			0x7fff0000
3398 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR			0x0000209c
3399 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE	0x80000000
3400 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK			0x00007fff
3401 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT			0
3406 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK			0x7fff0000
3413 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL			0x0000209d
3414 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE	0x80000000
3415 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK			0x00007fff
3416 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT			0
3421 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK			0x7fff0000
3428 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR			0x0000209e
3429 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE	0x80000000
3430 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK			0x00007fff
3431 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT			0
3436 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK			0x7fff0000
3443 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL			0x0000209f
3444 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE	0x80000000
3445 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK			0x00007fff
3446 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT			0
3451 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK			0x7fff0000
3458 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL			0x00000e80
3460 #define REG_A4XX_UCHE_TRAP_BASE_LO				0x00000e83
3462 #define REG_A4XX_UCHE_TRAP_BASE_HI				0x00000e84
3464 #define REG_A4XX_UCHE_CACHE_STATUS				0x00000e88
3466 #define REG_A4XX_UCHE_INVALIDATE0				0x00000e8a
3468 #define REG_A4XX_UCHE_INVALIDATE1				0x00000e8b
3470 #define REG_A4XX_UCHE_CACHE_WAYS_VFD				0x00000e8c
3472 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0			0x00000e8e
3474 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1			0x00000e8f
3476 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2			0x00000e90
3478 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3			0x00000e91
3480 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4			0x00000e92
3482 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5			0x00000e93
3484 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6			0x00000e94
3486 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7			0x00000e95
3488 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD				0x00000e00
3490 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL				0x00000e04
3492 #define REG_A4XX_HLSQ_MODE_CONTROL				0x00000e05
3494 #define REG_A4XX_HLSQ_PERF_PIPE_MASK				0x00000e0e
3496 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0			0x00000e06
3498 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1			0x00000e07
3500 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2			0x00000e08
3502 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3			0x00000e09
3504 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4			0x00000e0a
3506 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5			0x00000e0b
3508 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6			0x00000e0c
3510 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7			0x00000e0d
3512 #define REG_A4XX_HLSQ_CONTROL_0_REG				0x000023c0
3513 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK		0x00000010
3519 #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE		0x00000040
3520 #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART			0x00000200
3521 #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2			0x00000400
3522 #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE			0x04000000
3523 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK			0x08000000
3529 #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE		0x10000000
3530 #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE		0x20000000
3531 #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE			0x40000000
3532 #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT			0x80000000
3534 #define REG_A4XX_HLSQ_CONTROL_1_REG				0x000023c1
3535 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK		0x00000040
3541 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE		0x00000100
3542 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1			0x00000200
3543 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK		0x00ff0000
3549 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK		0xff000000
3556 #define REG_A4XX_HLSQ_CONTROL_2_REG				0x000023c2
3557 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK	0xfc000000
3563 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK			0x000003fc
3569 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK		0x0003fc00
3575 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK		0x03fc0000
3582 #define REG_A4XX_HLSQ_CONTROL_3_REG				0x000023c3
3583 #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK		0x000000ff
3584 #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT		0
3589 #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK		0x0000ff00
3595 #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK		0x00ff0000
3601 #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK	0xff000000
3608 #define REG_A4XX_HLSQ_CONTROL_4_REG				0x000023c4
3609 #define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK		0x000000ff
3610 #define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT		0
3615 #define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK		0x0000ff00
3622 #define REG_A4XX_HLSQ_VS_CONTROL_REG				0x000023c5
3623 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK		0x000000ff
3624 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT		0
3629 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK	0x00007f00
3635 #define A4XX_HLSQ_VS_CONTROL_REG_SSBO_ENABLE			0x00008000
3636 #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED			0x00010000
3637 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK		0x00fe0000
3643 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK		0xff000000
3650 #define REG_A4XX_HLSQ_FS_CONTROL_REG				0x000023c6
3651 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK		0x000000ff
3652 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT		0
3657 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK	0x00007f00
3663 #define A4XX_HLSQ_FS_CONTROL_REG_SSBO_ENABLE			0x00008000
3664 #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED			0x00010000
3665 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK		0x00fe0000
3671 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK		0xff000000
3678 #define REG_A4XX_HLSQ_HS_CONTROL_REG				0x000023c7
3679 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK		0x000000ff
3680 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT		0
3685 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK	0x00007f00
3691 #define A4XX_HLSQ_HS_CONTROL_REG_SSBO_ENABLE			0x00008000
3692 #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED			0x00010000
3693 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK		0x00fe0000
3699 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK		0xff000000
3706 #define REG_A4XX_HLSQ_DS_CONTROL_REG				0x000023c8
3707 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK		0x000000ff
3708 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT		0
3713 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK	0x00007f00
3719 #define A4XX_HLSQ_DS_CONTROL_REG_SSBO_ENABLE			0x00008000
3720 #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED			0x00010000
3721 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK		0x00fe0000
3727 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK		0xff000000
3734 #define REG_A4XX_HLSQ_GS_CONTROL_REG				0x000023c9
3735 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK		0x000000ff
3736 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT		0
3741 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK	0x00007f00
3747 #define A4XX_HLSQ_GS_CONTROL_REG_SSBO_ENABLE			0x00008000
3748 #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED			0x00010000
3749 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK		0x00fe0000
3755 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK		0xff000000
3762 #define REG_A4XX_HLSQ_CS_CONTROL_REG				0x000023ca
3763 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK		0x000000ff
3764 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT		0
3769 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK	0x00007f00
3775 #define A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE			0x00008000
3776 #define A4XX_HLSQ_CS_CONTROL_REG_ENABLED			0x00010000
3777 #define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK		0x00fe0000
3783 #define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK		0xff000000
3790 #define REG_A4XX_HLSQ_CL_NDRANGE_0				0x000023cd
3791 #define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK			0x00000003
3792 #define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT			0
3797 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK			0x00000ffc
3803 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK			0x003ff000
3809 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK			0xffc00000
3816 #define REG_A4XX_HLSQ_CL_NDRANGE_1				0x000023ce
3817 #define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK			0xffffffff
3818 #define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT			0
3824 #define REG_A4XX_HLSQ_CL_NDRANGE_2				0x000023cf
3826 #define REG_A4XX_HLSQ_CL_NDRANGE_3				0x000023d0
3827 #define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK			0xffffffff
3828 #define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT			0
3834 #define REG_A4XX_HLSQ_CL_NDRANGE_4				0x000023d1
3836 #define REG_A4XX_HLSQ_CL_NDRANGE_5				0x000023d2
3837 #define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK			0xffffffff
3838 #define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT			0
3844 #define REG_A4XX_HLSQ_CL_NDRANGE_6				0x000023d3
3846 #define REG_A4XX_HLSQ_CL_CONTROL_0				0x000023d4
3847 #define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK		0x00000fff
3848 #define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT		0
3853 #define A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__MASK		0x00fff000
3859 #define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK		0xff000000
3866 #define REG_A4XX_HLSQ_CL_CONTROL_1				0x000023d5
3867 #define A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__MASK		0x00000fff
3868 #define A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__SHIFT		0
3873 #define A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__MASK	0x00fff000
3880 #define REG_A4XX_HLSQ_CL_KERNEL_CONST				0x000023d6
3881 #define A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__MASK		0x00000fff
3882 #define A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__SHIFT		0
3887 #define A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__MASK		0x00fff000
3894 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X				0x000023d7
3896 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y				0x000023d8
3898 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z				0x000023d9
3900 #define REG_A4XX_HLSQ_CL_WG_OFFSET				0x000023da
3901 #define A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__MASK		0x00000fff
3902 #define A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__SHIFT		0
3908 #define REG_A4XX_HLSQ_UPDATE_CONTROL				0x000023db
3910 #define REG_A4XX_PC_BINNING_COMMAND				0x00000d00
3911 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE			0x00000001
3913 #define REG_A4XX_PC_TESSFACTOR_ADDR				0x00000d08
3915 #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE			0x00000d0c
3917 #define REG_A4XX_PC_PERFCTR_PC_SEL_0				0x00000d10
3919 #define REG_A4XX_PC_PERFCTR_PC_SEL_1				0x00000d11
3921 #define REG_A4XX_PC_PERFCTR_PC_SEL_2				0x00000d12
3923 #define REG_A4XX_PC_PERFCTR_PC_SEL_3				0x00000d13
3925 #define REG_A4XX_PC_PERFCTR_PC_SEL_4				0x00000d14
3927 #define REG_A4XX_PC_PERFCTR_PC_SEL_5				0x00000d15
3929 #define REG_A4XX_PC_PERFCTR_PC_SEL_6				0x00000d16
3931 #define REG_A4XX_PC_PERFCTR_PC_SEL_7				0x00000d17
3933 #define REG_A4XX_PC_BIN_BASE					0x000021c0
3935 #define REG_A4XX_PC_VSTREAM_CONTROL				0x000021c2
3936 #define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK			0x003f0000
3942 #define A4XX_PC_VSTREAM_CONTROL_N__MASK				0x07c00000
3949 #define REG_A4XX_PC_PRIM_VTX_CNTL				0x000021c4
3950 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK			0x0000000f
3951 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT			0
3956 #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART			0x00100000
3957 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST		0x02000000
3958 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE				0x04000000
3960 #define REG_A4XX_PC_PRIM_VTX_CNTL2				0x000021c5
3961 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK	0x00000007
3962 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT	0
3967 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK	0x00000038
3973 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE			0x00000040
3975 #define REG_A4XX_PC_RESTART_INDEX				0x000021c6
3977 #define REG_A4XX_PC_GS_PARAM					0x000021e5
3978 #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK			0x000003ff
3979 #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT			0
3984 #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK			0x0000f800
3990 #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK				0x01800000
3996 #define A4XX_PC_GS_PARAM_LAYER					0x80000000
3998 #define REG_A4XX_PC_HS_PARAM					0x000021e7
3999 #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK			0x0000003f
4000 #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT			0
4005 #define A4XX_PC_HS_PARAM_SPACING__MASK				0x00600000
4011 #define A4XX_PC_HS_PARAM_CW					0x00800000
4012 #define A4XX_PC_HS_PARAM_CONNECTED				0x01000000
4014 #define REG_A4XX_VBIF_VERSION					0x00003000
4016 #define REG_A4XX_VBIF_CLKON					0x00003001
4017 #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS			0x00000001
4019 #define REG_A4XX_VBIF_ABIT_SORT					0x0000301c
4021 #define REG_A4XX_VBIF_ABIT_SORT_CONF				0x0000301d
4023 #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN				0x0000302a
4025 #define REG_A4XX_VBIF_IN_RD_LIM_CONF0				0x0000302c
4027 #define REG_A4XX_VBIF_IN_RD_LIM_CONF1				0x0000302d
4029 #define REG_A4XX_VBIF_IN_WR_LIM_CONF0				0x00003030
4031 #define REG_A4XX_VBIF_IN_WR_LIM_CONF1				0x00003031
4033 #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB			0x00003049
4035 #define REG_A4XX_VBIF_PERF_CNT_EN0				0x000030c0
4037 #define REG_A4XX_VBIF_PERF_CNT_EN1				0x000030c1
4039 #define REG_A4XX_VBIF_PERF_CNT_EN2				0x000030c2
4041 #define REG_A4XX_VBIF_PERF_CNT_EN3				0x000030c3
4043 #define REG_A4XX_VBIF_PERF_CNT_SEL0				0x000030d0
4045 #define REG_A4XX_VBIF_PERF_CNT_SEL1				0x000030d1
4047 #define REG_A4XX_VBIF_PERF_CNT_SEL2				0x000030d2
4049 #define REG_A4XX_VBIF_PERF_CNT_SEL3				0x000030d3
4051 #define REG_A4XX_VBIF_PERF_CNT_LOW0				0x000030d8
4053 #define REG_A4XX_VBIF_PERF_CNT_LOW1				0x000030d9
4055 #define REG_A4XX_VBIF_PERF_CNT_LOW2				0x000030da
4057 #define REG_A4XX_VBIF_PERF_CNT_LOW3				0x000030db
4059 #define REG_A4XX_VBIF_PERF_CNT_HIGH0				0x000030e0
4061 #define REG_A4XX_VBIF_PERF_CNT_HIGH1				0x000030e1
4063 #define REG_A4XX_VBIF_PERF_CNT_HIGH2				0x000030e2
4065 #define REG_A4XX_VBIF_PERF_CNT_HIGH3				0x000030e3
4067 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN0				0x00003100
4069 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN1				0x00003101
4071 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN2				0x00003102
4073 #define REG_A4XX_UNKNOWN_0CC5					0x00000cc5
4075 #define REG_A4XX_UNKNOWN_0CC6					0x00000cc6
4077 #define REG_A4XX_UNKNOWN_0D01					0x00000d01
4079 #define REG_A4XX_UNKNOWN_0E42					0x00000e42
4081 #define REG_A4XX_UNKNOWN_0EC2					0x00000ec2
4083 #define REG_A4XX_UNKNOWN_2001					0x00002001
4085 #define REG_A4XX_UNKNOWN_209B					0x0000209b
4087 #define REG_A4XX_UNKNOWN_20EF					0x000020ef
4089 #define REG_A4XX_UNKNOWN_2152					0x00002152
4091 #define REG_A4XX_UNKNOWN_2153					0x00002153
4093 #define REG_A4XX_UNKNOWN_2154					0x00002154
4095 #define REG_A4XX_UNKNOWN_2155					0x00002155
4097 #define REG_A4XX_UNKNOWN_2156					0x00002156
4099 #define REG_A4XX_UNKNOWN_2157					0x00002157
4101 #define REG_A4XX_UNKNOWN_21C3					0x000021c3
4103 #define REG_A4XX_UNKNOWN_21E6					0x000021e6
4105 #define REG_A4XX_UNKNOWN_2209					0x00002209
4107 #define REG_A4XX_UNKNOWN_22D7					0x000022d7
4109 #define REG_A4XX_UNKNOWN_2352					0x00002352
4111 #define REG_A4XX_TEX_SAMP_0					0x00000000
4112 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR			0x00000001
4113 #define A4XX_TEX_SAMP_0_XY_MAG__MASK				0x00000006
4119 #define A4XX_TEX_SAMP_0_XY_MIN__MASK				0x00000018
4125 #define A4XX_TEX_SAMP_0_WRAP_S__MASK				0x000000e0
4131 #define A4XX_TEX_SAMP_0_WRAP_T__MASK				0x00000700
4137 #define A4XX_TEX_SAMP_0_WRAP_R__MASK				0x00003800
4143 #define A4XX_TEX_SAMP_0_ANISO__MASK				0x0001c000
4149 #define A4XX_TEX_SAMP_0_LOD_BIAS__MASK				0xfff80000
4156 #define REG_A4XX_TEX_SAMP_1					0x00000001
4157 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK			0x0000000e
4163 #define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF			0x00000010
4164 #define A4XX_TEX_SAMP_1_UNNORM_COORDS				0x00000020
4165 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR			0x00000040
4166 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK				0x000fff00
4172 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK				0xfff00000
4179 #define REG_A4XX_TEX_CONST_0					0x00000000
4180 #define A4XX_TEX_CONST_0_TILED					0x00000001
4181 #define A4XX_TEX_CONST_0_SRGB					0x00000004
4182 #define A4XX_TEX_CONST_0_SWIZ_X__MASK				0x00000070
4188 #define A4XX_TEX_CONST_0_SWIZ_Y__MASK				0x00000380
4194 #define A4XX_TEX_CONST_0_SWIZ_Z__MASK				0x00001c00
4200 #define A4XX_TEX_CONST_0_SWIZ_W__MASK				0x0000e000
4206 #define A4XX_TEX_CONST_0_MIPLVLS__MASK				0x000f0000
4212 #define A4XX_TEX_CONST_0_FMT__MASK				0x1fc00000
4218 #define A4XX_TEX_CONST_0_TYPE__MASK				0xe0000000
4225 #define REG_A4XX_TEX_CONST_1					0x00000001
4226 #define A4XX_TEX_CONST_1_HEIGHT__MASK				0x00007fff
4227 #define A4XX_TEX_CONST_1_HEIGHT__SHIFT				0
4232 #define A4XX_TEX_CONST_1_WIDTH__MASK				0x3fff8000
4239 #define REG_A4XX_TEX_CONST_2					0x00000002
4240 #define A4XX_TEX_CONST_2_PITCHALIGN__MASK			0x0000000f
4241 #define A4XX_TEX_CONST_2_PITCHALIGN__SHIFT			0
4246 #define A4XX_TEX_CONST_2_BUFFER					0x00000040
4247 #define A4XX_TEX_CONST_2_PITCH__MASK				0x3ffffe00
4253 #define A4XX_TEX_CONST_2_SWAP__MASK				0xc0000000
4260 #define REG_A4XX_TEX_CONST_3					0x00000003
4261 #define A4XX_TEX_CONST_3_LAYERSZ__MASK				0x00003fff
4262 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT				0
4267 #define A4XX_TEX_CONST_3_DEPTH__MASK				0x7ffc0000
4274 #define REG_A4XX_TEX_CONST_4					0x00000004
4275 #define A4XX_TEX_CONST_4_LAYERSZ__MASK				0x0000000f
4276 #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT				0
4281 #define A4XX_TEX_CONST_4_BASE__MASK				0xffffffe0
4288 #define REG_A4XX_TEX_CONST_5					0x00000005
4290 #define REG_A4XX_TEX_CONST_6					0x00000006
4292 #define REG_A4XX_TEX_CONST_7					0x00000007
4294 #define REG_A4XX_SSBO_0_0					0x00000000
4295 #define A4XX_SSBO_0_0_BASE__MASK				0xffffffe0
4302 #define REG_A4XX_SSBO_0_1					0x00000001
4303 #define A4XX_SSBO_0_1_PITCH__MASK				0x003fffff
4304 #define A4XX_SSBO_0_1_PITCH__SHIFT				0
4310 #define REG_A4XX_SSBO_0_2					0x00000002
4311 #define A4XX_SSBO_0_2_ARRAY_PITCH__MASK				0x03fff000
4318 #define REG_A4XX_SSBO_0_3					0x00000003
4319 #define A4XX_SSBO_0_3_CPP__MASK					0x0000003f
4320 #define A4XX_SSBO_0_3_CPP__SHIFT				0
4326 #define REG_A4XX_SSBO_1_0					0x00000000
4327 #define A4XX_SSBO_1_0_CPP__MASK					0x0000001f
4328 #define A4XX_SSBO_1_0_CPP__SHIFT				0
4333 #define A4XX_SSBO_1_0_FMT__MASK					0x0000ff00
4339 #define A4XX_SSBO_1_0_WIDTH__MASK				0xffff0000
4346 #define REG_A4XX_SSBO_1_1					0x00000001
4347 #define A4XX_SSBO_1_1_HEIGHT__MASK				0x0000ffff
4348 #define A4XX_SSBO_1_1_HEIGHT__SHIFT				0
4353 #define A4XX_SSBO_1_1_DEPTH__MASK				0xffff0000