105 	writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0,  in meson_viu_set_g12a_osd1_matrix()
149 		writel_bits_relaxed(3 << 30, m[21] << 30,  in meson_viu_set_osd_matrix()
151 		writel_bits_relaxed(7 << 16, m[22] << 16,  in meson_viu_set_osd_matrix()
155 		writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0,  in meson_viu_set_osd_matrix()
157 		writel_bits_relaxed(BIT(1), 0,  in meson_viu_set_osd_matrix()
168 		writel_bits_relaxed(BIT(30), csc_on ? BIT(30) : 0,  in meson_viu_set_osd_matrix()
170 		writel_bits_relaxed(BIT(31), csc_on ? BIT(31) : 0,  in meson_viu_set_osd_matrix()
221 			writel_bits_relaxed(0x7 << 29, 7 << 29,  in meson_viu_set_osd_lut()
224 			writel_bits_relaxed(0x7 << 29, 0,  in meson_viu_set_osd_lut()
248 			writel_bits_relaxed(7 << 27, 7 << 27,  in meson_viu_set_osd_lut()
251 			writel_bits_relaxed(7 << 27, 0,  in meson_viu_set_osd_lut()
254 		writel_bits_relaxed(BIT(31), BIT(31),  in meson_viu_set_osd_lut()
326 	writel_bits_relaxed(VIU_SW_RESET_OSD1, VIU_SW_RESET_OSD1,  in meson_viu_osd1_reset()
328 	writel_bits_relaxed(VIU_SW_RESET_OSD1, 0,  in meson_viu_osd1_reset()
366 	writel_bits_relaxed(VIU_OSD1_MALI_UNPACK_EN,  in meson_viu_g12a_enable_osd1_afbc()
378 	writel_bits_relaxed(VIU_OSD1_MALI_AFBCD_A_REORDER |  in meson_viu_g12a_enable_osd1_afbc()
386 	writel_bits_relaxed(OSD_PATH_OSD_AXI_SEL_OSD1_AFBCD,  in meson_viu_g12a_enable_osd1_afbc()
394 	writel_bits_relaxed(OSD_PATH_OSD_AXI_SEL_OSD1_AFBCD, 0,  in meson_viu_g12a_disable_osd1_afbc()
398 	writel_bits_relaxed(VIU_OSD1_MALI_UNPACK_EN, 0,  in meson_viu_g12a_disable_osd1_afbc()
404 	writel_bits_relaxed(MALI_AFBC_MISC, FIELD_PREP(MALI_AFBC_MISC, 0x90),  in meson_viu_gxm_enable_osd1_afbc()
410 	writel_bits_relaxed(MALI_AFBC_MISC, FIELD_PREP(MALI_AFBC_MISC, 0x00),  in meson_viu_gxm_disable_osd1_afbc()
419 	writel_bits_relaxed(VIU_OSD1_OSD_BLK_ENABLE | VIU_OSD1_OSD_ENABLE, 0,  in meson_viu_init()
421 	writel_bits_relaxed(VIU_OSD1_OSD_BLK_ENABLE | VIU_OSD1_OSD_ENABLE, 0,  in meson_viu_init()
432 		writel_bits_relaxed(OSD1_HDR2_CTRL_REG_ONLY_MAT |  in meson_viu_init()
452 	writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,  in meson_viu_init()
455 	writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,  in meson_viu_init()
461 	writel_bits_relaxed(VIU_CTRL0_VD1_AFBC_MASK, 0,  in meson_viu_init()
494 		writel_bits_relaxed(DOLBY_BYPASS_EN(0xc), DOLBY_BYPASS_EN(0xc),  in meson_viu_init()