143 	void __iomem *hdmitx;  member
170 	writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);  in dw_hdmi_top_read()
171 	writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);  in dw_hdmi_top_read()
174 	data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG);  in dw_hdmi_top_read()
175 	data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG);  in dw_hdmi_top_read()
185 	return readl(dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2));  in dw_hdmi_g12a_top_read()
196 	writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);  in dw_hdmi_top_write()
197 	writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);  in dw_hdmi_top_write()
200 	writel(data, dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG);  in dw_hdmi_top_write()
208 	writel(data, dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2));  in dw_hdmi_g12a_top_write()
234 	writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);  in dw_hdmi_dwc_read()
235 	writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);  in dw_hdmi_dwc_read()
238 	data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG);  in dw_hdmi_dwc_read()
239 	data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG);  in dw_hdmi_dwc_read()
249 	return readb(dw_hdmi->hdmitx + addr);  in dw_hdmi_g12a_dwc_read()
260 	writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);  in dw_hdmi_dwc_write()
261 	writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);  in dw_hdmi_dwc_write()
264 	writel(data, dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG);  in dw_hdmi_dwc_write()
272 	writeb(data, dw_hdmi->hdmitx + addr);  in dw_hdmi_g12a_dwc_write()
630 				    meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG);  in meson_dw_hdmi_init()
632 				    meson_dw_hdmi->hdmitx + HDMITX_DWC_CTRL_REG);  in meson_dw_hdmi_init()
738 	meson_dw_hdmi->hdmitx = devm_platform_ioremap_resource(pdev, 0);  in meson_dw_hdmi_bind()
739 	if (IS_ERR(meson_dw_hdmi->hdmitx))  in meson_dw_hdmi_bind()
740 		return PTR_ERR(meson_dw_hdmi->hdmitx);  in meson_dw_hdmi_bind()