Lines Matching refs:DDC_DDCMCTL1
35 #define DDC_DDCMCTL1 (0x4) macro
106 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK, in ddcm_trigger_mode()
108 sif_set_bit(ddc, DDC_DDCMCTL1, DDCM_TRI); in ddcm_trigger_mode()
109 readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val, in ddcm_trigger_mode()
123 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET, in mtk_hdmi_ddc_read_msg()
126 ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET); in mtk_hdmi_ddc_read_msg()
147 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, in mtk_hdmi_ddc_read_msg()
153 ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, in mtk_hdmi_ddc_read_msg()
196 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET, in mtk_hdmi_ddc_write_msg()
200 ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET); in mtk_hdmi_ddc_write_msg()
228 if (sif_bit_is_set(ddc, DDC_DDCMCTL1, DDCM_TRI)) { in mtk_hdmi_ddc_xfer()