drm/mediatek/mtk_dp.c

122 	struct mtk_dp_train_info train_info;
1158 			.ssc = mtk_dp->train_info.sink_ssc,
1319 	mtk_dp->train_info.link_rate = DP_LINK_BW_5_4;
1320 	mtk_dp->train_info.lane_count = mtk_dp->max_lanes;
1321 	mtk_dp->train_info.cable_plugged_in = plugged_in;
1339 				    mtk_dp->train_info.link_rate * 2700 * 8 /
1342 	switch (mtk_dp->train_info.lane_count) {
1375 	switch (mtk_dp->train_info.lane_count) {
1386 		if (pix_clk_mhz > mtk_dp->train_info.link_rate * 27)
1401 				    mtk_dp->train_info.lane_count /
1455 		aux_offset = mtk_dp->train_info.channel_eq_pattern;
1457 		switch (mtk_dp->train_info.channel_eq_pattern) {
1486 	if (mtk_dp->train_info.sink_ssc)
1515 		if (!mtk_dp->train_info.cable_plugged_in) {
1583 		if (!mtk_dp->train_info.cable_plugged_in) {
1630 	    mtk_dp->train_info.sink_ssc)
1638 		mtk_dp->train_info.channel_eq_pattern = DP_TRAINING_PATTERN_4;
1640 		mtk_dp->train_info.channel_eq_pattern = DP_TRAINING_PATTERN_3;
1642 		mtk_dp->train_info.channel_eq_pattern = DP_TRAINING_PATTERN_2;
1644 	mtk_dp->train_info.sink_ssc = drm_dp_max_downspread(mtk_dp->rx_cap);
1764 	mtk_dp->train_info.link_rate = link_rate;
1765 	mtk_dp->train_info.lane_count = lane_count;
1859 	if (mtk_dp->need_debounce && mtk_dp->train_info.cable_plugged_in)
1871 		if (!mtk_dp->train_info.cable_plugged_in) {
1915 			mtk_dp->train_info.cable_plugged_in = true;
1917 			mtk_dp->train_info.cable_plugged_in = false;
1933 		mtk_dp->train_info.cable_plugged_in = false;
1937 	mtk_dp->train_info.cable_plugged_in = true;
2007 	if (!mtk_dp->train_info.cable_plugged_in)
2097 	    !mtk_dp->train_info.cable_plugged_in) {
2292 	if (mtk_dp->train_info.cable_plugged_in) {