drm/mediatek/mtk_dp.c

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2019-2022 MediaTek Inc.
18 #include <linux/arm-smccc.h>
23 #include <linux/media-bus-format.h>
24 #include <linux/nvmem-consumer.h>
33 #include <sound/hdmi-codec.h>
317 	.name = "mtk-dp-registers",
330 	ret = regmap_read(mtk_dp->regs, offset, &read_val);
332 		dev_err(mtk_dp->dev, "Failed to read register 0x%x: %d\n",
342 	int ret = regmap_write(mtk_dp->regs, offset, val);
345 		dev_err(mtk_dp->dev,
354 	int ret = regmap_update_bits(mtk_dp->regs, offset, mask, val);
357 		dev_err(mtk_dp->dev,
391 	struct videomode *vm = &mtk_dp->info.vm;
399 			   vm->hsync_len + vm->hback_porch,
402 			   vm->hsync_len, HSW_SW_DP_ENC0_P0_MASK);
406 			   vm->hactive, HWIDTH_SW_DP_ENC0_P0_MASK);
412 			   vm->vsync_len + vm->vback_porch,
415 			   vm->vsync_len, VSW_SW_DP_ENC0_P0_MASK);
419 			   vm->vactive, VHEIGHT_SW_DP_ENC0_P0_MASK);
423 			   vm->hactive, HDE_NUM_LAST_DP_ENC0_P0_MASK);
427 			   vm->hfront_porch,
430 			   vm->hsync_len,
433 			   vm->hback_porch + vm->hsync_len,
436 			   vm->hactive,
444 			   vm->vfront_porch,
447 			   vm->vsync_len,
450 			   vm->vback_porch + vm->vsync_len,
453 			   vm->vactive,
473 		drm_warn(mtk_dp->drm_dev, "Unsupported color format: %d\n",
475 		return -EINVAL;
562 	switch (cfg->channels) {
595 	switch (cfg->sample_rate) {
619 	switch (cfg->word_length_bits) {
648 			   (min(8, channels) - 1) << 8,
676 	u32 db_addr = MTK_DP_ENC0_P0_30D8 + (MTK_DP_SDP_AUI - 1) * 8;
693 	mtk_dp_sdp_set_data(mtk_dp, sdp->db);
694 	mtk_dp_sdp_set_header_aui(mtk_dp, &sdp->sdp_header);
766 				   (length - 1) << 12,
786 	while (--wait_reply) {
804 			return -ETIMEDOUT;
810 	return -ETIMEDOUT;
820 		return -EINVAL;
855 			dev_err(mtk_dp->dev,
857 			return -EIO;
860 		return -ETIMEDOUT;
889 	dev_dbg(mtk_dp->dev,
890 		"link training: swing_val = 0x%x, pre-emphasis = 0x%x\n",
1070 	struct device *dev = mtk_dp->dev;
1072 	u32 *cal_data = mtk_dp->cal_data;
1096 		fmt = &mtk_dp->data->efuse_fmt[i];
1097 		cal_data[i] = (buf[fmt->idx] >> fmt->shift) & fmt->mask;
1099 		if (cal_data[i] < fmt->min_val || cal_data[i] > fmt->max_val) {
1100 			dev_warn(mtk_dp->dev, "Invalid efuse data, idx = %d\n", i);
1110 	dev_warn(mtk_dp->dev, "Use default calibration data\n");
1112 		cal_data[i] = mtk_dp->data->efuse_fmt[i].default_val;
1117 	u32 *cal_data = mtk_dp->cal_data;
1161 			.ssc = mtk_dp->train_info.sink_ssc,
1168 	ret = phy_configure(mtk_dp->phy, &phy_opts);
1198 			   pattern ? BIT(pattern - 1) << 12 : 0,
1231 		      mtk_dp->data->smc_cmd, enable,
1234 	dev_dbg(mtk_dp->dev, "smc cmd: 0x%x, p1: %s, ret: 0x%lx-0x%lx\n",
1235 		mtk_dp->data->smc_cmd, enable ? "enable" : "disable", res.a0, res.a1);
1273 		drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
1277 		drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3);
1320 	bool plugged_in = (mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP);
1322 	mtk_dp->train_info.link_rate = DP_LINK_BW_5_4;
1323 	mtk_dp->train_info.lane_count = mtk_dp->max_lanes;
1324 	mtk_dp->train_info.cable_plugged_in = plugged_in;
1326 	mtk_dp->info.format = DP_PIXELFORMAT_RGB;
1327 	memset(&mtk_dp->info.vm, 0, sizeof(struct videomode));
1328 	mtk_dp->audio_enable = false;
1336 	struct videomode *vm = &mtk_dp->info.vm;
1342 				    mtk_dp->train_info.link_rate * 2700 * 8 /
1345 	switch (mtk_dp->train_info.lane_count) {
1371 	struct videomode *vm = &mtk_dp->info.vm;
1375 	pix_clk_mhz = mtk_dp->info.format == DP_PIXELFORMAT_YUV420 ?
1378 	switch (mtk_dp->train_info.lane_count) {
1389 		if (pix_clk_mhz > mtk_dp->train_info.link_rate * 27)
1403 				    mtk_dp->info.vm.hactive /
1404 				    mtk_dp->train_info.lane_count /
1444 		drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_LANE0_SET + lane,
1458 		aux_offset = mtk_dp->train_info.channel_eq_pattern;
1460 		switch (mtk_dp->train_info.channel_eq_pattern) {
1477 	drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET, aux_offset);
1485 	drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LINK_BW_SET, target_link_rate);
1486 	drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET,
1489 	if (mtk_dp->train_info.sink_ssc)
1490 		drm_dp_dpcd_writeb(&mtk_dp->aux, DP_DOWNSPREAD_CTRL,
1498 	dev_dbg(mtk_dp->dev,
1518 		if (!mtk_dp->train_info.cable_plugged_in) {
1520 			return -ENODEV;
1523 		drm_dp_dpcd_read(&mtk_dp->aux, DP_ADJUST_REQUEST_LANE0_1,
1528 		drm_dp_link_train_clock_recovery_delay(&mtk_dp->aux,
1529 						       mtk_dp->rx_cap);
1532 		drm_dp_dpcd_read_link_status(&mtk_dp->aux, link_status);
1535 			dev_dbg(mtk_dp->dev, "Link train CR pass\n");
1551 			 *    level and reach max voltage level (3).
1555 				dev_dbg(mtk_dp->dev, "Link train CR fail\n");
1561 			 * re-calculate this retry count.
1569 	drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET,
1573 	return -ETIMEDOUT;
1586 		if (!mtk_dp->train_info.cable_plugged_in) {
1588 			return -ENODEV;
1591 		drm_dp_dpcd_read(&mtk_dp->aux, DP_ADJUST_REQUEST_LANE0_1,
1596 		drm_dp_link_train_channel_eq_delay(&mtk_dp->aux,
1597 						   mtk_dp->rx_cap);
1600 		drm_dp_dpcd_read_link_status(&mtk_dp->aux, link_status);
1602 			dev_dbg(mtk_dp->dev, "Link train EQ pass\n");
1605 			drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET,
1610 		dev_dbg(mtk_dp->dev, "Link train EQ fail\n");
1614 	drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET,
1618 	return -ETIMEDOUT;
1631 	if (mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP &&
1632 	    mtk_dp->rx_cap[DP_MAX_LINK_RATE] &&
1633 	    mtk_dp->train_info.sink_ssc)
1636 	ret = drm_dp_read_dpcd_caps(&mtk_dp->aux, mtk_dp->rx_cap);
1640 	if (drm_dp_tps4_supported(mtk_dp->rx_cap))
1641 		mtk_dp->train_info.channel_eq_pattern = DP_TRAINING_PATTERN_4;
1642 	else if (drm_dp_tps3_supported(mtk_dp->rx_cap))
1643 		mtk_dp->train_info.channel_eq_pattern = DP_TRAINING_PATTERN_3;
1645 		mtk_dp->train_info.channel_eq_pattern = DP_TRAINING_PATTERN_2;
1647 	mtk_dp->train_info.sink_ssc = drm_dp_max_downspread(mtk_dp->rx_cap);
1649 	ret = drm_dp_dpcd_readb(&mtk_dp->aux, DP_MSTM_CAP, &val);
1651 		drm_err(mtk_dp->drm_dev, "Read mstm cap failed\n");
1652 		return ret == 0 ? -EIO : ret;
1657 		ret = drm_dp_dpcd_readb(&mtk_dp->aux,
1661 			drm_err(mtk_dp->drm_dev, "Read irq vector failed\n");
1662 			return ret == 0 ? -EIO : ret;
1666 			ret = drm_dp_dpcd_writeb(&mtk_dp->aux,
1680 	if (!mtk_dp->data->audio_supported)
1683 	if (mtk_dp->info.audio_cur_cfg.sad_count <= 0) {
1684 		drm_info(mtk_dp->drm_dev, "The SADs is NULL\n");
1693 	phy_reset(mtk_dp->phy);
1702 	link_rate = min_t(u8, mtk_dp->max_linkrate,
1703 			  mtk_dp->rx_cap[DP_MAX_LINK_RATE]);
1705 	lane_count = min_t(u8, mtk_dp->max_lanes,
1706 			   drm_dp_max_lane_count(mtk_dp->rx_cap));
1715 	for (train_limit = 6; train_limit > 0; train_limit--) {
1723 		if (ret == -ENODEV) {
1732 					return -EIO;
1744 				return -EINVAL;
1750 		if (ret == -ENODEV) {
1755 				return -EIO;
1765 		return -ETIMEDOUT;
1767 	mtk_dp->train_info.link_rate = link_rate;
1768 	mtk_dp->train_info.lane_count = lane_count;
1803 	frame.channels = cfg->channels;
1804 	frame.sample_frequency = cfg->sample_rate;
1806 	switch (cfg->word_length_bits) {
1821 	mtk_dp_audio_sdp_asp_set_channels(mtk_dp, cfg->channels);
1840 	return mtk_dp_set_color_format(mtk_dp, mtk_dp->info.format);
1862 	if (mtk_dp->need_debounce && mtk_dp->train_info.cable_plugged_in)
1865 	spin_lock_irqsave(&mtk_dp->irq_thread_lock, flags);
1866 	status = mtk_dp->irq_thread_handle;
1867 	mtk_dp->irq_thread_handle = 0;
1868 	spin_unlock_irqrestore(&mtk_dp->irq_thread_lock, flags);
1871 		if (mtk_dp->bridge.dev)
1872 			drm_helper_hpd_irq_event(mtk_dp->bridge.dev);
1874 		if (!mtk_dp->train_info.cable_plugged_in) {
1876 			memset(&mtk_dp->info.audio_cur_cfg, 0,
1877 			       sizeof(mtk_dp->info.audio_cur_cfg));
1879 			mtk_dp->need_debounce = false;
1880 			mod_timer(&mtk_dp->debounce_timer,
1881 				  jiffies + msecs_to_jiffies(100) - 1);
1886 		dev_dbg(mtk_dp->dev, "Receive IRQ from sink devices\n");
1902 	spin_lock_irqsave(&mtk_dp->irq_thread_lock, flags);
1905 		mtk_dp->irq_thread_handle |= MTK_DP_THREAD_HPD_EVENT;
1909 		mtk_dp->irq_thread_handle |= MTK_DP_THREAD_CABLE_STATE_CHG;
1913 	spin_unlock_irqrestore(&mtk_dp->irq_thread_lock, flags);
1918 			mtk_dp->train_info.cable_plugged_in = true;
1920 			mtk_dp->train_info.cable_plugged_in = false;
1932 	ret = regmap_read_poll_timeout(mtk_dp->regs, MTK_DP_TRANS_P0_3414,
1936 		mtk_dp->train_info.cable_plugged_in = false;
1940 	mtk_dp->train_info.cable_plugged_in = true;
1944 		drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n");
1955 	struct device *dev = &pdev->dev;
1958 	u32 linkrate;
1965 	mtk_dp->regs = devm_regmap_init_mmio(dev, base, &mtk_dp_regmap_config);
1966 	if (IS_ERR(mtk_dp->regs))
1967 		return PTR_ERR(mtk_dp->regs);
1969 	endpoint = of_graph_get_endpoint_by_regs(pdev->dev.of_node, 1, -1);
1971 					      "data-lanes", sizeof(u32));
1974 		return -EINVAL;
1977 	mtk_dp->max_lanes = len;
1979 	ret = device_property_read_u32(dev, "max-linkrate-mhz", &linkrate);
1981 		dev_err(dev, "failed to read max linkrate: %d\n", ret);
1985 	mtk_dp->max_linkrate = drm_dp_link_rate_to_bw_code(linkrate * 100);
1992 	if (!mtk_dp->data->audio_supported || !mtk_dp->audio_enable)
1995 	mutex_lock(&mtk_dp->update_plugged_status_lock);
1996 	if (mtk_dp->plugged_cb && mtk_dp->codec_dev)
1997 		mtk_dp->plugged_cb(mtk_dp->codec_dev,
1998 				   mtk_dp->enabled &
1999 				   mtk_dp->info.audio_cur_cfg.detect_monitor);
2000 	mutex_unlock(&mtk_dp->update_plugged_status_lock);
2007 	bool enabled = mtk_dp->enabled;
2009 	if (!mtk_dp->train_info.cable_plugged_in)
2023 	if (drm_dp_read_sink_count(&mtk_dp->aux) > 0)
2036 	bool enabled = mtk_dp->enabled;
2038 	struct mtk_dp_audio_cfg *audio_caps = &mtk_dp->info.audio_cur_cfg;
2041 		drm_atomic_bridge_chain_pre_enable(bridge, connector->state->state);
2045 	drm_edid = drm_edid_read_ddc(connector, &mtk_dp->aux.ddc);
2052 		drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n");
2071 		audio_caps->sad_count = ret;
2074 		 * FIXME: This should use connector->display_info.has_audio from
2078 		audio_caps->detect_monitor = drm_detect_monitor_audio(edid);
2083 		drm_atomic_bridge_chain_post_disable(bridge, connector->state->state);
2098 	if (mtk_dp->bridge.type != DRM_MODE_CONNECTOR_eDP &&
2099 	    !mtk_dp->train_info.cable_plugged_in) {
2100 		ret = -EIO;
2104 	switch (msg->request) {
2110 		request = msg->request & ~DP_AUX_I2C_WRITE_STATUS_UPDATE;
2116 		request = msg->request;
2120 		dev_err(mtk_dp->dev, "invalid aux cmd = %d\n",
2121 			msg->request);
2122 		ret = -EINVAL;
2128 					 msg->size - accessed_bytes);
2131 					     msg->address + accessed_bytes,
2132 					     msg->buffer + accessed_bytes,
2133 					     to_access, &msg->reply);
2136 			dev_info(mtk_dp->dev,
2141 	} while (accessed_bytes < msg->size);
2143 	return msg->size;
2145 	msg->reply = DP_AUX_NATIVE_REPLY_NACK | DP_AUX_I2C_REPLY_NACK;
2153 	ret = phy_init(mtk_dp->phy);
2155 		dev_err(mtk_dp->dev, "Failed to initialize phy: %d\n", ret);
2168 	phy_exit(mtk_dp->phy);
2178 		dev_err(mtk_dp->dev, "Driver does not provide a connector!");
2179 		return -EINVAL;
2182 	mtk_dp->aux.drm_dev = bridge->dev;
2183 	ret = drm_dp_aux_register(&mtk_dp->aux);
2185 		dev_err(mtk_dp->dev,
2194 	if (mtk_dp->next_bridge) {
2195 		ret = drm_bridge_attach(bridge->encoder, mtk_dp->next_bridge,
2196 					&mtk_dp->bridge, flags);
2198 			drm_warn(mtk_dp->drm_dev,
2204 	mtk_dp->drm_dev = bridge->dev;
2206 	if (mtk_dp->bridge.type != DRM_MODE_CONNECTOR_eDP) {
2207 		irq_clear_status_flags(mtk_dp->irq, IRQ_NOAUTOEN);
2208 		enable_irq(mtk_dp->irq);
2217 	drm_dp_aux_unregister(&mtk_dp->aux);
2225 	if (mtk_dp->bridge.type != DRM_MODE_CONNECTOR_eDP) {
2227 		disable_irq(mtk_dp->irq);
2229 	mtk_dp->drm_dev = NULL;
2231 	drm_dp_aux_unregister(&mtk_dp->aux);
2240 	mtk_dp->conn = drm_atomic_get_new_connector_for_encoder(old_state->base.state,
2241 								bridge->encoder);
2242 	if (!mtk_dp->conn) {
2243 		drm_err(mtk_dp->drm_dev,
2253 		drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret);
2263 	mtk_dp->audio_enable =
2265 						     &mtk_dp->info.audio_cur_cfg);
2266 	if (mtk_dp->audio_enable) {
2267 		mtk_dp_audio_setup(mtk_dp, &mtk_dp->info.audio_cur_cfg);
2270 		memset(&mtk_dp->info.audio_cur_cfg, 0,
2271 		       sizeof(mtk_dp->info.audio_cur_cfg));
2274 	mtk_dp->enabled = true;
2289 	mtk_dp->enabled = false;
2294 	if (mtk_dp->train_info.cable_plugged_in) {
2295 		drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3);
2314 	u32 bpp = info->color_formats & DRM_COLOR_FORMAT_YCBCR422 ? 16 : 24;
2315 	u32 lane_count_min = mtk_dp->train_info.lane_count;
2316 	u32 rate = drm_dp_bw_code_to_link_rate(mtk_dp->train_info.link_rate) *
2321 	 *The down-spread amplitude shall either be disabled (0.0%) or up
2325 	 *mode->clock does not need to be multiplied by 10
2327 	if ((rate * 97 / 100) < (mode->clock * bpp / 8))
2365 	struct drm_display_mode *mode = &crtc_state->adjusted_mode;
2367 		&conn_state->connector->display_info;
2368 	u32 lane_count_min = mtk_dp->train_info.lane_count;
2369 	u32 rate = drm_dp_bw_code_to_link_rate(mtk_dp->train_info.link_rate) *
2375 	 * If the linkrate is smaller than datarate of RGB888, larger than
2379 	if (((rate * 97 / 100) < (mode->clock * 24 / 8)) &&
2380 	    ((rate * 97 / 100) > (mode->clock * 16 / 8)) &&
2381 	    (display_info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
2407 	struct drm_crtc *crtc = conn_state->crtc;
2410 	input_bus_format = bridge_state->input_bus_cfg.format;
2412 	dev_dbg(mtk_dp->dev, "input format 0x%04x, output format 0x%04x\n",
2413 		bridge_state->input_bus_cfg.format,
2414 		 bridge_state->output_bus_cfg.format);
2417 		mtk_dp->info.format = DP_PIXELFORMAT_YUV422;
2419 		mtk_dp->info.format = DP_PIXELFORMAT_RGB;
2422 		drm_err(mtk_dp->drm_dev,
2424 		return -EINVAL;
2427 	drm_display_mode_to_videomode(&crtc_state->adjusted_mode, &mtk_dp->info.vm);
2452 	mtk_dp->need_debounce = true;
2464 	if (!mtk_dp->enabled) {
2465 		dev_err(mtk_dp->dev, "%s, DP is not ready!\n", __func__);
2466 		return -ENODEV;
2469 	mtk_dp->info.audio_cur_cfg.channels = params->cea.channels;
2470 	mtk_dp->info.audio_cur_cfg.sample_rate = params->sample_rate;
2472 	mtk_dp_audio_setup(mtk_dp, &mtk_dp->info.audio_cur_cfg);
2498 	if (mtk_dp->enabled)
2499 		memcpy(buf, mtk_dp->conn->eld, len);
2512 	mutex_lock(&mtk_dp->update_plugged_status_lock);
2513 	mtk_dp->plugged_cb = fn;
2514 	mtk_dp->codec_dev = codec_dev;
2515 	mutex_unlock(&mtk_dp->update_plugged_status_lock);
2541 	mtk_dp->audio_pdev = platform_device_register_data(dev,
2546 	return PTR_ERR_OR_ZERO(mtk_dp->audio_pdev);
2551 	struct device *dev = mtk_dp->dev;
2553 	mtk_dp->phy_dev = platform_device_register_data(dev, "mediatek-dp-phy",
2555 							&mtk_dp->regs,
2557 	if (IS_ERR(mtk_dp->phy_dev))
2558 		return dev_err_probe(dev, PTR_ERR(mtk_dp->phy_dev),
2559 				     "Failed to create device mediatek-dp-phy\n");
2563 	mtk_dp->phy = devm_phy_get(&mtk_dp->phy_dev->dev, "dp");
2564 	if (IS_ERR(mtk_dp->phy)) {
2565 		platform_device_unregister(mtk_dp->phy_dev);
2566 		return dev_err_probe(dev, PTR_ERR(mtk_dp->phy), "Failed to get phy\n");
2575 	struct device *dev = mtk_aux->dev;
2578 	mtk_dp->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
2586 	if (IS_ERR(mtk_dp->next_bridge)) {
2587 		ret = PTR_ERR(mtk_dp->next_bridge);
2588 		mtk_dp->next_bridge = NULL;
2593 	ret = devm_drm_bridge_add(dev, &mtk_dp->bridge);
2603 	struct device *dev = &pdev->dev;
2608 		return -ENOMEM;
2610 	mtk_dp->dev = dev;
2611 	mtk_dp->data = (struct mtk_dp_data *)of_device_get_match_data(dev);
2624 	if (mtk_dp->data->bridge_type != DRM_MODE_CONNECTOR_eDP) {
2625 		mtk_dp->irq = platform_get_irq(pdev, 0);
2626 		if (mtk_dp->irq < 0)
2627 			return dev_err_probe(dev, mtk_dp->irq,
2630 		spin_lock_init(&mtk_dp->irq_thread_lock);
2632 		irq_set_status_flags(mtk_dp->irq, IRQ_NOAUTOEN);
2633 		ret = devm_request_threaded_irq(dev, mtk_dp->irq, mtk_dp_hpd_event,
2641 		mtk_dp->need_debounce = true;
2642 		timer_setup(&mtk_dp->debounce_timer, mtk_dp_debounce_timer, 0);
2645 	mtk_dp->aux.name = "aux_mtk_dp";
2646 	mtk_dp->aux.dev = dev;
2647 	mtk_dp->aux.transfer = mtk_dp_aux_transfer;
2648 	mtk_dp->aux.wait_hpd_asserted = mtk_dp_wait_hpd_asserted;
2649 	drm_dp_aux_init(&mtk_dp->aux);
2653 	if (mtk_dp->data->audio_supported) {
2654 		mutex_init(&mtk_dp->update_plugged_status_lock);
2668 	mtk_dp->bridge.funcs = &mtk_dp_bridge_funcs;
2669 	mtk_dp->bridge.of_node = dev->of_node;
2670 	mtk_dp->bridge.type = mtk_dp->data->bridge_type;
2672 	if (mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP) {
2686 		 * Power on the AUX to allow reading the EDID from aux-bus:
2695 		ret = devm_of_dp_aux_populate_bus(&mtk_dp->aux, mtk_dp_edp_link_panel);
2697 			/* -ENODEV this means that the panel is not on the aux-bus */
2698 			if (ret == -ENODEV) {
2699 				ret = mtk_dp_edp_link_panel(&mtk_dp->aux);
2711 		mtk_dp->bridge.ops = DRM_BRIDGE_OP_DETECT |
2713 		ret = devm_drm_bridge_add(dev, &mtk_dp->bridge);
2728 	pm_runtime_put(&pdev->dev);
2729 	pm_runtime_disable(&pdev->dev);
2730 	if (mtk_dp->data->bridge_type != DRM_MODE_CONNECTOR_eDP)
2731 		del_timer_sync(&mtk_dp->debounce_timer);
2732 	platform_device_unregister(mtk_dp->phy_dev);
2733 	if (mtk_dp->audio_pdev)
2734 		platform_device_unregister(mtk_dp->audio_pdev);
2743 	if (mtk_dp->bridge.type != DRM_MODE_CONNECTOR_eDP)
2756 	if (mtk_dp->bridge.type != DRM_MODE_CONNECTOR_eDP)
2782 		.compatible = "mediatek,mt8195-edp-tx",
2786 		.compatible = "mediatek,mt8195-dp-tx",
2797 		.name = "mediatek-drm-dp",
2806 MODULE_AUTHOR("Markus Schneider-Pargmann <msp@baylibre.com>");
2807 MODULE_AUTHOR("Bo-Chen Chen <rex-bc.chen@mediatek.com>");