1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <linux/soc/mediatek/mtk-cmdq.h>
31 #define OVL_BGCLR_SEL_IN				BIT(2)
47 #define DISP_REG_OVL_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n))  argument
48 #define DISP_REG_OVL_HDR_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n) + 0x04)  argument
49 #define DISP_REG_OVL_HDR_PITCH(ovl, n)		((ovl)->data->addr + 0x20 * (n) + 0x08)  argument
58 #define OVL_CON_CLRFMT_RGBA8888	(2 << 12)
62 #define OVL_CON_CLRFMT_RGB565(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \  argument
64 #define OVL_CON_CLRFMT_RGB888(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \  argument
66 #define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl)	(0xFF << 4 * (ovl))  argument
67 #define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl)	(depth << 4 * (ovl))  argument
120  * struct mtk_disp_ovl - DISP_OVL driver structure
139 	writel(0x0, priv->regs + DISP_REG_OVL_INTSTA);  in mtk_disp_ovl_irq_handler()
141 	if (!priv->vblank_cb)  in mtk_disp_ovl_irq_handler()
144 	priv->vblank_cb(priv->vblank_cb_data);  in mtk_disp_ovl_irq_handler()
153 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_register_vblank_cb()  local
155 	ovl->vblank_cb = vblank_cb;  in mtk_ovl_register_vblank_cb()
156 	ovl->vblank_cb_data = vblank_cb_data;  in mtk_ovl_register_vblank_cb()
161 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_unregister_vblank_cb()  local
163 	ovl->vblank_cb = NULL;  in mtk_ovl_unregister_vblank_cb()
164 	ovl->vblank_cb_data = NULL;  in mtk_ovl_unregister_vblank_cb()
169 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_enable_vblank()  local
171 	writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);  in mtk_ovl_enable_vblank()
172 	writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN);  in mtk_ovl_enable_vblank()
177 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_disable_vblank()  local
179 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);  in mtk_ovl_disable_vblank()
184 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_get_formats()  local
186 	return ovl->data->formats;  in mtk_ovl_get_formats()
191 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_get_num_formats()  local
193 	return ovl->data->num_formats;  in mtk_ovl_get_num_formats()
198 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_clk_enable()  local
200 	return clk_prepare_enable(ovl->clk);  in mtk_ovl_clk_enable()
205 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_clk_disable()  local
207 	clk_disable_unprepare(ovl->clk);  in mtk_ovl_clk_disable()
212 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_start()  local
214 	if (ovl->data->smi_id_en) {  in mtk_ovl_start()
217 		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_start()
219 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_start()
221 	writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);  in mtk_ovl_start()
226 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_stop()  local
228 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);  in mtk_ovl_stop()
229 	if (ovl->data->smi_id_en) {  in mtk_ovl_stop()
232 		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_stop()
234 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_stop()
238 static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt,  in mtk_ovl_set_afbc()  argument
242 			   &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_set_afbc()
249 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_set_bit_depth()  local
253 	if (!ovl->data->supports_clrfmt_ext)  in mtk_ovl_set_bit_depth()
256 	reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT);  in mtk_ovl_set_bit_depth()
266 	mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg,  in mtk_ovl_set_bit_depth()
267 		      ovl->regs, DISP_REG_OVL_CLRFMT_EXT);  in mtk_ovl_set_bit_depth()
274 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_config()  local
277 		mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_config()
284 	mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl->cmdq_reg,  in mtk_ovl_config()
285 			      ovl->regs, DISP_REG_OVL_ROI_BGCLR);  in mtk_ovl_config()
287 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);  in mtk_ovl_config()
288 	mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);  in mtk_ovl_config()
293 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_layer_nr()  local
295 	return ovl->data->layer_nr;  in mtk_ovl_layer_nr()
307 	struct drm_plane_state *state = &mtk_state->base;  in mtk_ovl_layer_check()
310 	rotation = drm_rotation_simplify(state->rotation,  in mtk_ovl_layer_check()
318 		return -EINVAL;  in mtk_ovl_layer_check()
324 	if (state->fb->format->is_yuv && rotation != 0)  in mtk_ovl_layer_check()
325 		return -EINVAL;  in mtk_ovl_layer_check()
327 	state->rotation = rotation;  in mtk_ovl_layer_check()
338 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_layer_on()  local
340 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_on()
343 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);  in mtk_ovl_layer_on()
345 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);  in mtk_ovl_layer_on()
346 	if (ovl->data->gmc_bits == 10)  in mtk_ovl_layer_on()
352 		      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));  in mtk_ovl_layer_on()
353 	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_on()
360 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_layer_off()  local
362 	mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_off()
364 	mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_off()
368 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)  in ovl_fmt_convert()  argument
378 		return OVL_CON_CLRFMT_RGB565(ovl);  in ovl_fmt_convert()
380 		return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP;  in ovl_fmt_convert()
382 		return OVL_CON_CLRFMT_RGB888(ovl);  in ovl_fmt_convert()
384 		return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;  in ovl_fmt_convert()
406 static void mtk_ovl_afbc_layer_config(struct mtk_disp_ovl *ovl,  in mtk_ovl_afbc_layer_config()  argument
411 	unsigned int pitch_msb = pending->pitch >> 16;  in mtk_ovl_afbc_layer_config()
412 	unsigned int hdr_pitch = pending->hdr_pitch;  in mtk_ovl_afbc_layer_config()
413 	unsigned int hdr_addr = pending->hdr_addr;  in mtk_ovl_afbc_layer_config()
415 	if (pending->modifier != DRM_FORMAT_MOD_LINEAR) {  in mtk_ovl_afbc_layer_config()
416 		mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_afbc_layer_config()
417 				      DISP_REG_OVL_HDR_ADDR(ovl, idx));  in mtk_ovl_afbc_layer_config()
420 				      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));  in mtk_ovl_afbc_layer_config()
421 		mtk_ddp_write_relaxed(cmdq_pkt, hdr_pitch, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_afbc_layer_config()
422 				      DISP_REG_OVL_HDR_PITCH(ovl, idx));  in mtk_ovl_afbc_layer_config()
425 				      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));  in mtk_ovl_afbc_layer_config()
433 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_layer_config()  local
434 	struct mtk_plane_pending_state *pending = &state->pending;  in mtk_ovl_layer_config()
435 	unsigned int addr = pending->addr;  in mtk_ovl_layer_config()
436 	unsigned int pitch_lsb = pending->pitch & GENMASK(15, 0);  in mtk_ovl_layer_config()
437 	unsigned int fmt = pending->format;  in mtk_ovl_layer_config()
438 	unsigned int offset = (pending->y << 16) | pending->x;  in mtk_ovl_layer_config()
439 	unsigned int src_size = (pending->height << 16) | pending->width;  in mtk_ovl_layer_config()
443 	if (!pending->enable) {  in mtk_ovl_layer_config()
448 	con = ovl_fmt_convert(ovl, fmt);  in mtk_ovl_layer_config()
449 	if (state->base.fb && state->base.fb->format->has_alpha)  in mtk_ovl_layer_config()
453 	 * can be ignored, or OVL will still read the value from memory.  in mtk_ovl_layer_config()
457 	if (state->base.fb && !state->base.fb->format->has_alpha)  in mtk_ovl_layer_config()
460 	if (pending->rotation & DRM_MODE_REFLECT_Y) {  in mtk_ovl_layer_config()
462 		addr += (pending->height - 1) * pending->pitch;  in mtk_ovl_layer_config()
465 	if (pending->rotation & DRM_MODE_REFLECT_X) {  in mtk_ovl_layer_config()
467 		addr += pending->pitch - 1;  in mtk_ovl_layer_config()
470 	if (ovl->data->supports_afbc)  in mtk_ovl_layer_config()
471 		mtk_ovl_set_afbc(ovl, cmdq_pkt, idx,  in mtk_ovl_layer_config()
472 				 pending->modifier != DRM_FORMAT_MOD_LINEAR);  in mtk_ovl_layer_config()
474 	mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
477 			      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx));  in mtk_ovl_layer_config()
478 	mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
480 	mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
482 	mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
483 			      DISP_REG_OVL_ADDR(ovl, idx));  in mtk_ovl_layer_config()
485 	if (ovl->data->supports_afbc)  in mtk_ovl_layer_config()
486 		mtk_ovl_afbc_layer_config(ovl, idx, pending, cmdq_pkt);  in mtk_ovl_layer_config()
494 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_bgclr_in_on()  local
497 	reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_on()
499 	writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_on()
504 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);  in mtk_ovl_bgclr_in_off()  local
507 	reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_off()
509 	writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_off()
530 	struct device *dev = &pdev->dev;  in mtk_disp_ovl_probe()
538 		return -ENOMEM;  in mtk_disp_ovl_probe()
544 	priv->clk = devm_clk_get(dev, NULL);  in mtk_disp_ovl_probe()
545 	if (IS_ERR(priv->clk)) {  in mtk_disp_ovl_probe()
546 		dev_err(dev, "failed to get ovl clk\n");  in mtk_disp_ovl_probe()
547 		return PTR_ERR(priv->clk);  in mtk_disp_ovl_probe()
551 	priv->regs = devm_ioremap_resource(dev, res);  in mtk_disp_ovl_probe()
552 	if (IS_ERR(priv->regs)) {  in mtk_disp_ovl_probe()
553 		dev_err(dev, "failed to ioremap ovl\n");  in mtk_disp_ovl_probe()
554 		return PTR_ERR(priv->regs);  in mtk_disp_ovl_probe()
557 	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);  in mtk_disp_ovl_probe()
559 		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");  in mtk_disp_ovl_probe()
562 	priv->data = of_device_get_match_data(dev);  in mtk_disp_ovl_probe()
585 	component_del(&pdev->dev, &mtk_disp_ovl_component_ops);  in mtk_disp_ovl_remove()
586 	pm_runtime_disable(&pdev->dev);  in mtk_disp_ovl_remove()
619 	.layer_nr = 2,
638 	.layer_nr = 2,
658 	{ .compatible = "mediatek,mt2701-disp-ovl",
660 	{ .compatible = "mediatek,mt8173-disp-ovl",
662 	{ .compatible = "mediatek,mt8183-disp-ovl",
664 	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
666 	{ .compatible = "mediatek,mt8192-disp-ovl",
668 	{ .compatible = "mediatek,mt8192-disp-ovl-2l",
670 	{ .compatible = "mediatek,mt8195-disp-ovl",
680 		.name	= "mediatek-disp-ovl",