160 	framesize = FIELD_PREP(IMX21LCDC_LSR_XMAX, crtc->mode.hdisplay >> 4) |  in imx_lcdc_update_hw_registers()
161 		FIELD_PREP(IMX21LCDC_LSR_YMAX, crtc->mode.vdisplay);  in imx_lcdc_update_hw_registers()
165 	lhcr = FIELD_PREP(IMX21LCDC_LHCR_HFPORCH, crtc->mode.hsync_start - crtc->mode.hdisplay - 1) |  in imx_lcdc_update_hw_registers()
166 		FIELD_PREP(IMX21LCDC_LHCR_HWIDTH, crtc->mode.hsync_end - crtc->mode.hsync_start - 1) |  in imx_lcdc_update_hw_registers()
167 		FIELD_PREP(IMX21LCDC_LHCR_HBPORCH, crtc->mode.htotal - crtc->mode.hsync_end - 3);  in imx_lcdc_update_hw_registers()
171 	lvcr = FIELD_PREP(IMX21LCDC_LVCR_VFPORCH, crtc->mode.vsync_start - crtc->mode.vdisplay) |  in imx_lcdc_update_hw_registers()
172 		FIELD_PREP(IMX21LCDC_LVCR_VWIDTH, crtc->mode.vsync_end - crtc->mode.vsync_start) |  in imx_lcdc_update_hw_registers()
173 		FIELD_PREP(IMX21LCDC_LVCR_VBPORCH, crtc->mode.vtotal - crtc->mode.vsync_end);  in imx_lcdc_update_hw_registers()
197 	struct drm_display_mode *mode = &pipe->crtc.mode;  in imx_lcdc_pipe_enable()  local
199 	const int hsync_pol = (mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : 1;  in imx_lcdc_pipe_enable()
200 	const int vsync_pol = (mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : 1;  in imx_lcdc_pipe_enable()
207 					mode->clock * 1000);  in imx_lcdc_pipe_enable()
278 	const struct drm_display_mode *mode = &crtc_state->mode;  in imx_lcdc_pipe_check()  local
279 	const struct drm_display_mode *old_mode = &pipe->crtc.state->mode;  in imx_lcdc_pipe_check()
281 	if (mode->hdisplay < LCDC_MIN_XRES || mode->hdisplay > LCDC_MAX_XRES ||  in imx_lcdc_pipe_check()
282 	    mode->vdisplay < LCDC_MIN_YRES || mode->vdisplay > LCDC_MAX_YRES ||  in imx_lcdc_pipe_check()
283 	    mode->hdisplay % 0x10) { /* must be multiple of 16 */  in imx_lcdc_pipe_check()
285 			mode->hdisplay, mode->vdisplay);  in imx_lcdc_pipe_check()
290 		old_mode->hdisplay != mode->hdisplay ||  in imx_lcdc_pipe_check()
291 		old_mode->vdisplay != mode->vdisplay;  in imx_lcdc_pipe_check()